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datasheet r01ds0216ej0102 rev.1.02 page 1 of 121 dec 01, 2014 rx113 group renesas mcus features 32-bit rx cpu core ? 32 mhz maximum operating frequency capable of 50 dmips when operating at 32 mhz ? accumulator handle s 64-bit results (for a si ngle instruction) from 32-bit 32-b it operations ? multiplication and division unit handles 32-bit 32-bit operations (multiplication instruc tions take one cpu clock cycle) ? fast interrupt ? cisc harvard architecture with five-stage pipeline ? variable-length instruction format, ultra-compact code ? on-chip debugging circuit low power consumption functions ? operation from a single 1.8 to 3.6 v supply ? three low power consumption modes ? supply current high-speed operating mode: 0.11 ma/mhz software standby mode: 0.44 a ? recovery time from software standby mode: 4.8 s on-chip flash memory for code, no wait states ? operation at 32 mhz, read cycle of 31.25 ns ? no wait states for reading at full cpu speed ? 128 to 512 kbyte capacities ? programmable at 1.8 v ? for instructions and operands on-chip data flash memory ? 8 kbytes 1,000,000 erase/write cycles (typ.) ? bgo (background operation) on-chip sram, no wait states ? 32 and 64 kbyte capacities data transfer controller (dtc) ? four transfer modes ? transfer can be set for each interrupt source. event link controller (elc) ? module operation can be initiated by event signal s without going through interrupts. ? link operation between modules is possible while the cpu is sleeping. reset and power supply voltage management ? six types including power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? external clock input frequency: up to 20 mhz ? main clock oscillator frequency: 1 to 20 mhz ? sub-clock oscillator frequency: 32.768 khz ? pll circuit input: 4 to 8 mhz ? low-speed on-chip oscillator: 4 mhz ? high-speed on-chip oscillator: 32 mhz 1% ( ? 20 to 85c) ? iwdt-dedicated on-chip oscillator: 15 khz ? usb-dedicated pll circuit: 6 and 8 mhz ? generate a dedicated 32.768-khz clock for the rtc ? on-chip clock frequency accuracy measurement circuit (cac) realtime clock (rtc) ? 30-second, leap year, and error adjustment functions ? calendar count mode or bi nary count mode selectable ? capable of initiating exit fr om software standby mode independent watchdog timer (iwdt) ? 15-khz on-chip oscillator produces a dedicated clock signal to drive iwdt operation. on-chip functions for iec 60730 compliance ? clock frequency accuracy measurem ent circuit, iwdt, functions to assist in ram testing, etc. up to 12 channels for communication ? usb: usb 2.0 host/function/on -the-go (otg) (one channel), full-speed = 12 mbps, low-speed = 1.5 mbps, isochronous transfer, and bc (battery charger) supported ? sci: asynchronous mode, clock synchronous mode, smart card interface (up to eight channels) ? irda interface (one channel, in cooperation with sci5) ? i 2 c bus interface: transfer at up to 400 kbps, capable of smbus operation (one channel) ? rspi: up to 16 mbps (one channel) ? serial sound interface (ssi) (one channel) up to 14 extend ed-function timers ? 16-bit mtu: input capture/out put compare, complementary pwm output, phase counting mode (six channels) ? 8-bit tmr (four channels) ? 16-bit cmt (four channels) lcd controller/driver ? segment signal output common signal output: 40 4, 36 8 ? on-chip voltage boost circuit, contrast adjustment, and 5-v panel supported ? blinking function 12-bit a/d converter ? up to 17 channels ? 1.0 s minimum conversion speed ? double trigger (data duplicati on) function for motor control 12-bit d/a converter ? two channels comparator b ? two channels capacitive touch sensing unit (ctsu) ? detection pins: 12 channels (for 100 pins only) ? high-sensitive electrostatic capacitance detection using self-capacitance and mutual capacitance methods ? on-chip noise canceller that enable s high tolerance to disturbance noise ? also supports a mutu al capacitance method that allows touch channels to be increased with low pin counts temperature sensor general i/o ports ? 5-v tolerant, open drain, input pull-up multi-function pi n controller (mpc) ? multiple i/o pins can be select ed for peripheral functions. unique id ? 32-byte id code for the mcu operating temperature range ?? 40 to ?85? c ?? 40 to ? 105c plqp0100kb-a 14 14 mm, 0.5 mm pitch plqp0064kb-a 10 10 mm, 0.5 mm pitch ptlg0100ja-a 7 7 mm, 0.65 mm pitch 32 mhz 32-bit rx mcus, 50 dmips, up to 512 kbyt es of flash memory, usb 2.0 full-speed host/function/ot g, up to 12 comms channels, serial sound interface, lcd controller/driver, capaci tive touch sensing unit, 12- bit a/d, 12-bit d/a, rtc r01ds0216ej0102 rev.1.02 dec 01, 2014
r01ds0216ej0102 rev.1.02 page 2 of 121 dec 01, 2014 rx113 group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications, and table 1.2 gives a comparison of the functions of the products in different packages. table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the p ackage type. for details, see table 1.2, comparison of functions for different packages . table 1.1 outline of specifications (1/3) classification module/function description cpu cpu ? maximum operating frequency: 32 mhz ? 32-bit rx cpu ? minimum instruction execution time: one instruction per clock cycle ? address space: 4-gbyte linear ? register set general purpose: sixteen 32-bit registers control: eight 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32-bit 32-bit 64-bit ? on-chip divider: 32-bit 32-bit 32 bits ? barrel shifter: 32 bits memory rom ? capacity: 128 k /256 k /384 k /512 kbytes ? 32 mhz, no-wait memory access ? programming/erasing method: serial programming (asynchronous serial communication/usb communication), self-programming ram ? capacity: 32 k /64 kbytes ? 32 mhz, no-wait memory access e2 dataflash ? capacity: 8 kbytes ? number of erase/write cycles: 1,000,000 (typ) mcu operating mode single-chip mode clock clock generation circuit ? main clock oscillator, sub-clock oscillator, low-s peed on-chip oscillator, high-speed on-chip oscillator, pll frequency synthesizer, usb-dedicated pll frequency synthesizer, and iwdt-dedicated on-chip oscillator ? oscillation stop detection: available ? clock frequency accuracy measurement circuit (cac) ? independent settings for the system clock (iclk), peripheral module clock (pclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 32 mhz (at max.) peripheral modules run in synchronization with the pclk: 32 mhz (at max.) the flash peripheral circuit runs in sync hronization with the fclk: 32 mhz (at max.) ? the iclk frequency can only be set to fclk, pclkb, or pclkd multiplied by n (n: 1, 2, 4, 8, 16, 32, 64). resets res# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset voltage detection voltage detection circuit (lvdaa) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels low power consumption low power consumption functions ? module stop function ? three low power consumption modes sleep mode, deep sleep mode, and software standby mode function for lower operating power consumption ? operating power control modes high-speed operating mode, middle-speed operating mode, and low-speed operating mode interrupt interrupt controller (icub) ? interrupt vectors: 120 ? external interrupts: 9 (nmi, irq0 to irq7 pins) ? non-maskable interrupts: 4 (nmi pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority
r01ds0216ej0102 rev.1.02 page 3 of 121 dec 01, 2014 rx113 group 1. overview dma data transfer controller (dtca) ? transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 100-pin /64-pin ? i/o: 82/46 ? input: 2/2 ? pull-up resistors: 69/38 ? open-drain outputs: 61/34 ? 5-v tolerance: 4/4 event link controller (elc) ? event signals of 44 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for port b multi-function pin controller (mpc) capable of selecting the input/output function from multiple pins timers multi-function timer pulse unit 2 (mtu2a) ? (16 bits 6 channels) 1 unit ? time bases for the six 16-bit ti mer channels can be provided via up to 16 pulse-input/output lines and three pulse-input lines ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, mt clka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? capable of generating conversion start triggers for the a/d converter port output enable 2 (poe2a) controls the high-impedance state of the mtu?s waveform output pins compare match timer (cmt) ? (16 bits 2 channels) 2 units ? select from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) independent watchdog timer (iwdta) ? 14 bits 1 channel ? count clock: dedicated low-speed on-chip oscillator for the iwdt frequency divided by 1, 16, 32, 64, 128, or 256 realtime clock (rtca) ? clock source: sub-clock ? calendar count mode or binary count mode selectable ? interrupts: alarm interrupt, periodic interrupt, and carry interrupt 8-bit timer (tmr) ? (8 bits 2 channels) 2 units ? seven internal clocks (pclk/1, pclk/2, pclk/8, pclk/32, pclk/ 64, pclk/1024, and pclk/8192) and an external clock can be selected ? pulse output and pwm output with any duty cycle are available ? two channels can be cascaded and used as a 16-bit timer communication functions serial communications interfaces (scie, scif) ? 8 channels (channel 0, 1, 2, 5, 6, 8, and 9: scie, channel 12: scif) ? serial communications modes: asynchronous, clock synchronous, and smart card interface ? on -chip baud rate generator allows selection of the desired bit rate ? choice of lsb-fir s t or msb-first transfer ? average transfer rate clock can be input from mtu2 timers ? simple i 2 c ? simple spi ? master/slave mode supported (scif only) ? start frame and information frame are included (scif only) ? start-bit detection in asynchronous mode: low level or falling edge is selectable irda interface (irda) ? 1 channel (sci5 used) ? supports encoding/decoding of waveforms conforming to irda standard 1.0 i 2 c bus interface (riic) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master mode or slave mode selectable ? supports fast mode table 1.1 outline of specifications (2/3) classification module/function description
r01ds0216ej0102 rev.1.02 page 4 of 121 dec 01, 2014 rx113 group 1. overview communication functions serial peripheral interface (rspi) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (mast er in, slave out), ssl (slave select), and rspi clock (rspck) signals enables serial transfer through spi operation (four lines) or clock- synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception usb 2.0 host/function module (usbc) ? usb device controller (udc) and transceiver for usb 2.0 are incorporated. ? host/function module: 1 port ? compliant with usb version 2.0 ? transfer speed: full-speed (12 mbps), low-speed (1.5 mbps) ? otg (on-the-go) is supported. ? isochronous transfer is supported. ? bc (battery charger) is supported. serial sound interface (ssi) ? 1 channel ? capable of duplex communications ? various serial audio formats supported ? master/slave function supported ? programmable word clock or bit clock generation function ? 8/16/18/20/22/24/32-bit data formats supported ? on-chip 8-stage fifo for transmission/reception ? supports ws continue mode in which the ssiws signal is not stopped. lcd controller/driver (lcdc) ? internal voltage boosting method, capacitor split method, and external resistance division method are switchable. ? segment signal output common signal output: 40 4, 36 8 12-bit a/d converter (s12adb) ? 1 unit (1 unit 17 channels) ? 12-bit resolution ? minimum conversion time: 1.0 s per channel when the adclk is operating at 32 mhz ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) ? double trigger mode (duplication of a/d conversion data) ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu), an external trigger signal, or elc temperature sensor (tempsa) ? 1 channel ? the voltage of the temperature is converted into a digital value by the 12-bit a/d converter. 12-bit d/a converter (r12daa) ? 2 channels ? 12-bit resolution ? output voltage: 0.35 to avcc - 0.47 v crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. comparator b (cmpba) ? 2 channels ? function to compare the reference voltage and the analog input voltage ? window comparator operation or standard comparator operation is selectable capacitive touch sensing unit (ctsu) detect ion pin: 12 channels (for 100 pins only) data operation circuit (doc) comparison, addition, and subtraction of 16-bit data unique id 32-byte id code for the mcu power supply voltages/operating frequencies vcc = 1.8 to 2.4 v: 8 mhz, vcc = 2.4 to 2.7 v: 16 mhz, vcc = 2.7 to 3.6 v: 32 mhz supply current 3.6 ma at 32 mhz (typ.) operating temperature range d version: ? 40 to +85c, g version: ? 40 to +105c packages 100-pin lfqfp (plqp0100kb-a) 14 14 mm, 0.50 mm pitch 100-pin tflga (ptlg0100ja-a) 7 7 mm, 0.65 mm pitch 64-pin lfqfp (plqp0064kb-a) 10 10 mm, 0.50 mm pitch on-chip debugging system e1 emulator (fine interface) table 1.1 outline of specifications (3/3) classification module/function description
r01ds0216ej0102 rev.1.02 page 5 of 121 dec 01, 2014 rx113 group 1. overview table 1.2 comparison of functions for different packages module/functions rx113 group 100 pins 64 pins interrupts external interrupts nmi, irq0 to irq7 dma data transfer controller supported timers multi-function timer pulse unit 2 6 channels (mtu0 to mtu5) port output enable 2 supported compare match timer 2 channels 2 units realtime clock supported 8-bit timer 2 channels 2 units independent watchdog timer supported communication functions serial communications interfaces (scie) [simple i 2 c, simple spi] 7 channels (sci0, 1, 2, 5, 6, 8, 9) 5 channels (sci1, 5, 6, 8, 9) irda interface 1 channel (sci5) serial communications interface (scif) [simple i 2 c, simple spi] 1 channel (sci12) i 2 c bus interface 1 channel serial peripheral interface 1 channel usb 2.0 host/function module (usbc) 1 channel serial sound interface 1 channel 12-bit a/d converter (including high-precision channels) 17 channels (9 channels) 11 channels (3 channels) temperature sensor supported comparator b 2 channels 12-bit d/a converter 2 channels crc calculator supported event link controller supported capacitive touch sensing unit 12 channels not supported lcd 40 seg 4 com 36 seg 8 com 20 seg 4 com 16 seg 8 com packages 100-pin lfqfp 100-pin tflga 64-pin lfqfp
r01ds0216ej0102 rev.1.02 page 6 of 121 dec 01, 2014 rx113 group 1. overview 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product pa rt no., memory capacity, and package type. table 1.3 list of products group part no. orderable part no. package rom capacity ram capacity e2 dataflash maximum operating frequency operating temperature rx113 r5f51138adfp r5f51138adfp#3a plqp0100kb-a 512 kbytes 64 kbytes 8 kbytes 32mhz ? 40 to +85c r5f51138adfm r5f51138adfm#3a plqp0064kb-a r5f51138adlj r5f51138adlj#2a ptlg0100ja-a r5f51137adfp r5f51137adfp#3a plqp0100kb-a 384 kbytes r5f51137adfm r5f51137adfm#3a plqp0064kb-a r5f51137adlj r5f51137adlj#2a ptlg0100ja-a r5f51136adfp r5f51136adfp#3a plqp0100kb-a 256 kbytes 32 kbytes r5f51136adfm r5f51136adfm#3a plqp0064kb-a r5f51136adlj r5f51136adlj#2a ptlg0100ja-a r5f51135adfp r5f51135adfp#3a plqp0100kb-a 128 kbytes r5f51135adfm r5f51135adfm#3a plqp0064kb-a r5f51135adlj r5f51135adlj#2a ptlg0100ja-a r5f51138agfp r5f51138agfp#3a plqp0100kb-a 512 kbytes 64 kbytes ? 40 to +105c r5f51138agfm r5f51138agfm#3a plqp0064kb-a r5f51137agfp r5f51137agfp#3a plqp0100kb-a 384 kbytes r5f51137agfm r5f51137agfm#3a plqp0064kb-a r5f51136agfp r5f51136agfp#3a plqp0100kb-a 256 kbytes 32 kbytes r5f51136agfm r5f51136agfm#3a plqp0064kb-a r5f51135agfp r5f51135agfp#3a plqp0100kb-a 128 kbytes r5f51135agfm r5f51135agfm#3a plqp0064kb-a
r01ds0216ej0102 rev.1.02 page 7 of 121 dec 01, 2014 rx113 group 1. overview figure 1.1 how to read the product part no., memory capacity, and package type type of memory f: flash memory version package type, number of pins, and pin pitch fp: lfqfp/100/0.50 lj: tflga/100/0.65 fm: lfqfp/64/0.50 rom, ram, and e2 dataflash capacity 8: 512 kbytes/64 kbytes/8 kbytes 7: 384 kbytes/64 kbytes/8 kbytes 6: 256 kbytes/32 kbytes/8 kbytes 5: 128 kbytes/32 kbytes/8 kbytes group name 13: rx113 group renesas mcu renesas semiconductor product series name rx100 series d: operating temperat ure (-40c to +85c) g: operating temperature (-40c to +105c) r 5 f 5 1 d f m a83 1# 3 a packing, terminal ma terial (pb-free) #2: tray/sncu and others #3: tray/sn (tin) only production identification code
r01ds0216ej0102 rev.1.02 page 8 of 121 dec 01, 2014 rx113 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram icub: interrupt controller dtca: data transfer controller tmr: 8-bit timer iwdta: independent watchdog timer elc: event link controller crc: crc (cyclic redundancy check) calculator scie/scif: serial commu nications interface rspi: serial peripheral interface riic: i 2 c bus interface mtu2a: multi-function timer pulse unit 2 poe2a: port output enable 2 ssi: serial sound interface cmt: compare match timer rtcc: realtime clock doc: data operation circuit cac: clock frequency accuracy measurement circuit ctsu: capacitive touch sensing unit operand bus instruction bus internal main bus 1 clock generation circuit rx cpu ram rom port 0 port 1 port 3 port 4 12-bit d/a converter 2 channels riic 1 channel doc scie 7 channels (including irda 1 channel) e2 dataflash crc elc rtcc mtu2a 6 channels 12-bit a/d converter 17 channels cmt 2 channels (unit 0) rspi 1 channel internal main bus 2 dtca icub cac scif 1 channel port 5 port a port b port c port e port h poe2a iwdta ssi port 2 temperature sensor port j usb 2.0 host/function module comparator b lcd controller/driver ctsu internal peripheral buses 1 to 6 cmt 2 channels (unit 1) tmr 2 channels (unit 0) tmr 2 channels (unit 1) port 9 port d port f
r01ds0216ej0102 rev.1.02 page 9 of 121 dec 01, 2014 rx113 group 1. overview 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1/4) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl ? connect this pin to the vss pin via the 4.7 f smoothing capacitor used to stabilize the internal power supply. pl ace the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output/ input * 1 pins for connecting a crystal. an ex ternal clock can be input through the xtal pin. extal input xcin input input/output pins for the sub-clock oscillator. connec t a crystal between xcin and xcout. xcout output clkout output clock output pin. operating mode control md input pin for setting the operating mode. th e signal levels on this pin must not be changed during operation. ub# input pin used for boot mode (usb interface). upsel input pin used for boot mode (usb interface). system control res# input reset pin. this mcu enters the reset state when this signal goes low. cac cacref input input pin for the clock fr equency accuracy m easurement circuit. on-chip emulator fined i/o fine interface pin. lvd cmpa2 input detection target voltage pin for voltage detection 2. interrupts nmi input non-maskable interrupt request pin. irq0 to irq7 input interrupt request pins. multi-function timer pulse unit 2 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. port output enable 2 poe0# to poe3#, poe8# input input pins for request signals to place the mtu pins in the high impedance state. realtime clock rtcout output output pin for the 1-hz/64-hz clock. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for the external clock to be input to the counter. tmri0 to tmri3 input counter reset input pins.
r01ds0216ej0102 rev.1.02 page 10 of 121 dec 01, 2014 rx113 group 1. overview serial communications interface (scie) ? asynchronous mode/clock synchronous mode sck0, sck1, sck2, sck5, sck6, sck8, sck9 i/o input/output pins for the clock. rxd0, rxd1, rxd2, rxd5, rxd6, rxd8, rxd9 input input pins for received data. txd0, txd1, txd2, txd5, txd6, txd8, txd9 output output pins for transmitted data. cts0#, cts1#, cts2#, cts5#, cts6#, cts8#, cts9# input input pins for controlling the start of transmission and reception. rts0#, rts1#, rts2#, rts5#, rts6#, rts8#, rts9# output output pins for controlling th e start of transmission and reception. ? simple i 2 c mode sscl0, sscl1, sscl2, sscl5, sscl6, sscl8, sscl9 i/o input/output pins for the i 2 c clock. ssda0, ssda1, ssda2, ssda5, ssda6, ssda8, ssda9 i/o input/output pins for the i 2 c data. ? simple spi mode sck0, sck1, sck2, sck5, sck6, sck8, sck9 i/o input/output pins for the clock. smiso0, smiso1, smiso2, smiso5, smiso6, smiso8, smiso9 i/o input/output pins for slave transmit data. smosi0, smosi1, smosi2, smosi5, smosi6, smosi8, smosi9 i/o input/output pins for master transmit data. ss0#, ss1#, ss2#, ss5#, ss6#, ss8#, ss9# input chip-select input pins. irda interface irtxd5 output data output pin in the irda format. irrxd5 input data input pin in the irda format. serial communications interface (scif) ? asynchronous mode/clock synchronous mode sck12 i/o input/output pin for the clock. rxd12 input input pin for receiving data. txd12 output output pin for transmitting data. cts12# input input pin for controlling the start of transmission and reception. rts12# output output pin for controllin g the start of transmission and reception. ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock. ssda12 i/o input/output pin for the i 2 c data. ? simple spi mode sck12 i/o input/output pin for the clock. smiso12 i/o input/output pin for slave transmit data. smosi12 i/o input/output pin for master transmit data. ss12# input chip-select input pin. ? extended serial mode rxdx12 input input pin for data reception by scif. txdx12 output output pin for data transmission by scif. siox12 i/o input/output pin for data reception or transmission by scif. table 1.4 pin functions (2/4) classifications pin name i/o description
r01ds0216ej0102 rev.1.02 page 11 of 121 dec 01, 2014 rx113 group 1. overview i 2 c bus interface scl0 i/o input/output pin for i 2 c bus interface clocks. bus can be directly driven by the n-channel open drain output. sda0 i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open drain output. serial peripheral interface rspcka i/o input/output pin for the rspi clock. mosia i/o input/output pin for transmitting data from the rspi master. misoa i/o input/output pin for transmitting data from the rspi slave. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. serial sound interface ssisck0 i/o ssi serial bit clock pin. ssiws i/o word selection pin. ssitxd0 output serial data output pin. ssirxd0 input serial data input pin. audio_mclk input master clock pin for audio. usb 2.0 host/ function module vcc_usb input power supply pin for usb. connect this pin to vcc. vss_usb input ground pin for usb. connect this pin to vss. usb0_dp i/o d+ i/o pin of the usb on-chip transceiver. usb0_dm i/o d- i/o pin of the usb on-chip transceiver. usb0_vbus input usb cable connection monitor pin. usb0_exicen output low-power control signal for the otg chip. usb0_vbusen output vbus (5 v) supply enable signal for the otg chip. usb0_ovrcura, usb0_ovrcurb input external overcurrent detection pins. usb0_id input mini-ab connector id input pin during operation in otg mode. 12-bit a/d converter an000 to an015, an021 input input pins for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signals that start the a/d conversion. 12-bit d/a converter da0, da1 output output pins for the analog si gnals to be processed by the d/a converter. comparator b cmpb0 input input pin for the analog si gnal to be processed by comparator b0. cvrefb0 input analog reference voltage supply pin for comparator b0. cmpb1 input input pin for the analog signal to be processed by comparator b1. cvrefb1 input analog reference voltage supply pin for comparator b1. cmpob0 output output pin for comparator b0. cmpob1 output output pin for comparator b1. lcd vl1, vl2, vl3, vl4 i/o voltage pin for driving the lcd. caph, capl i/o capacitor connection pi n for the lcd controller/driver. com0 to com7 output common signal output pins for the lcd controller/driver. seg00 to seg39 output segment signal output pins for the lcd controller/driver. ctsu ts0 to ts11 input capacitive touch detection pins (touch pins). tscap i/o secondary power supply pin for the touch driver. table 1.4 pin functions (3/4) classifications pin name i/o description
r01ds0216ej0102 rev.1.02 page 12 of 121 dec 01, 2014 rx113 group 1. overview note 1. for external clock input. analog power supply avcc0 input analog voltage supply pin for the 12-bit a/d converter and d/a converter. connect this pin to vcc when not us ing the 12-bit a/d converter and d/a converter. avss0 input analog ground pin for the 12-bit a/d converter and d/a converter. connect this pin to vss when not using the 12- bit a/d converter and d/a converter. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. vrefl0 input analog reference ground pin for the 12-bit a/d converter. vrefh input analog reference voltage supply pin for the 12-bit d/a converter. vrefl input analog reference ground pin for the 12-bit d/a converter. i/o ports p02, p04, p07 i/o 3-bit input/output pins. p10 to p17 i/o 8-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p32, p35 i/o 4-bit input/output pins (p35 input pin). p40 to p44, p46 i/o 6-bit input/output pins. p50 to p56 i/o 7-bit input/output pins. p90 to p92 i/o 3-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd4 i/o 5-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. pf6, pf7 i/o 2-bit input/output pins. ph7 input 1-bit input pin. pj0, pj2, pj3, pj6, pj7 i/o 5-bit input/output pins. table 1.4 pin functions (4/4) classifications pin name i/o description
r01ds0216ej0102 rev.1.02 page 13 of 121 dec 01, 2014 rx113 group 1. overview 1.5 pin assignments figure 1.3 to figure 1.5 show the pin assignments. table 1.5 to table 1.7 show the lists of pins and pin functions. figure 1.3 pin assignments of the 100-pin lfqfp pe2 pe1 pe0 pe7 pe6 pd4 pd3 pd2 pd1 pd0 p46 p90 p44 p43 pe3 pe4 pe5 pf6 pf7 pa0 pa1 pa2 pa3 pa4 pa5 pa7 pa6 vss pb0 vcc pc2 pc3 pc4 pc5 pc6 pc7 p55 p50 p51 p52 p53 p56 p54 p10 p11 p12 p04 p26 p27 p30 p31 md res# xcout rx113 group plqp0100kb-a (100-pin lfqfp) (top view) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 81 82 78 76 77 79 80 83 84 85 86 87 88 90 91 89 17 18 19 20 21 22 23 24 25 p32 ph7/xcin p35/nmi xtal extal vcl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 59 58 57 56 55 54 53 52 51 p42/vrefl p41/vrefh pj7/vrefl0 pj6/vrefh0 avss0 avcc0 pj2 p13 vss_usb usb0_dp usb0_dm vcc_usb p14 p15 p16 p17 34 33 32 31 30 29 28 27 26 92 93 94 95 96 97 99 100 98 vcc vss p22 p23 p21 p20 pj3 p02 p25 p24 pj0 p07 p40 p92 p91 note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (100-pin lfqfp)?.
r01ds0216ej0102 rev.1.02 page 14 of 121 dec 01, 2014 rx113 group 1. overview figure 1.4 pin assignments of the 100-pin tflga p02 rx113 group ptlg0100ja-a (100-pin tflga) (upper perspective view) p25 pj3 p22 p30/ caph xcout xcin/ ph7 xtal vcl vss p07 p04 p24 p23 p31/ capl p35/ nmi p14 extal p17 vcc avcc0 pj2 pj6/ vrefh0 p21 p26 res# p12 p15 p32 p16 avss0 pj7/ vrefl0 p41/ vrefh pj0 p20 p27 md/ fined p13 vcc_ usb usb0_ dm p44 p90 p42/ vrefl p43 p40 p56 p10 p11 vss_ usb usb0_ dp p92 pd0 p91 p46 pa2 pb4 p50 p51 p52 p53 pd3 pd4 pd1 pf6 pa4 pa7 pb5 pc0 p55 p54 pe6 pe2 pd2 pf7 pa5 pb0 pb2 pc1 pc7 pc6 pb6 pe7 pe1 pe5 pa1 pa3 pa6 pb1 pc4 pc5 pe0 pe3 pe4 pa0 vss vcc pb3 pb7 pc2 pc3 abcdefghjk abcdefghjk 10 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (100-pin tflga)?.
r01ds0216ej0102 rev.1.02 page 15 of 121 dec 01, 2014 rx113 group 1. overview figure 1.5 pin assignments of the 64-pin lfqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx113 group plqp0064kb-a (64-pin lfqfp) (top view) pe2 pe1 pe0 pe7 pe6 pd2 pd1 pd0 p42 p41 pj7/vrefl0 p40 pj6/vrefh0 avss0 avcc0 pj2 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6/pc0 pb7/pc1 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 vss_usb usb0_dp usb0_dm vcc_usb p14 p15 p16 p17 pj0 p27 p26 p30 p31 md res# xcout ph7/xcin p35/nmi xtal extal vcl vss vcc p32 note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (64-pin lfqfp)?.
r01ds0216ej0102 rev.1.02 page 16 of 121 dec 01, 2014 rx113 group 1. overview table 1.5 list of pins and pin functions (100-pin lfqfp) (1/3) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others 1 p04 mtioc0a/poe2#/tmci3 sck6 ts1 2p j 0 da0 3 p02 mtioc0d/poe3#/tmri3 rxd6/smiso6/sscl6 ts2 4 pj3 mtioc3c cts6#/rts6#/ss6# ts3 5 p25 mtioc4c/mtclkb ts4 adtrg0# 6 p24 mtioc4a/mtclka/ tmri1 ts5 7 p23 mtioc3d/mtclkd cts0#/rts0#/ss0# ts6 8 p22 mtioc3b/mtclkc/ tmo0 sck0 ts7 9 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 ts8 10 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 ts9 11 p27 mtioc2b/tmci3 sck12/sck1/rxd6/smiso6/ sscl6 ts10 irq3/adtrg0#/ cacref/ cmpa2 12 p26 mtioc2a/tmo1 txd1/smosi1/ssda1/ usb0_vbusen/txd6/smosi6/ ssda6 tscap 13 p30 mtioc4b/poe8#/tmri3 rxd1/smiso1/sscl1 caph irq0 14 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# capl irq1 15 md fined 16 res# 17 xcout 18 xcin ph7 19 upsel p35 nmi 20 xtal 21 extal 22 vcl 23 vss 24 vdd 25 p32 mtioc0c/rtcout/ tmo3 txd6/smosi6/ssda6/cts6#/ rts6#/ss6# ts11 irq2 26 p17 mtioc0c/mtioc3a/ mtioc3b/poe8#/tmo1 sck1/misoa/sda0/rxd12/ rxdx12/smiso12/sscl12 irq7 27 p16 mtioc3c/mtioc3d/ rtcout/tmo2 txd1/smosi1/ssda1/mosia/ scl0/usb0_vbus/ usb0_vbusen/usb0_ovrcurb irq6/adtrg0# 28 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1/rspcka irq5/clkout/ cacref 29 ub# p14 mtioc0a/mtioc3a/ mtclka/tmri2 cts1#/rts1#/ss1#/ssla0/ txd12/txdx12/siox12/smosi12/ ssda12/usb0_ovrcura irq4 30 vcc_usb 31 usb0_dm 32 usb0_dp 33 vss_usb 34 p13 mtioc0b/tmo3 cts12#/rts12#/ss12#/cts0#/ rts0#/ss0# seg00 irq3 35 p12 tmci1 sck12/sck0 seg01 irq2
r01ds0216ej0102 rev.1.02 page 17 of 121 dec 01, 2014 rx113 group 1. overview 36 p11 mtic5u/poe0# rxd12/rxdx12/smiso12/ sscl12/ rxd0/smiso0/sscl0 seg02 irq7 37 p10 mtic5v/poe1# txd12/txdx12/siox12/smosi12/ ssda12/txd0/smosi0/ssda0 seg03 irq6 38 p56 mtioc1a/mtic5w/ poe2# txd1/smosi1/ssda1 seg04 irq5 39 p53 mtioc2b ssla0/cts2#/rts2#/ss2# seg05 40 p52 misoa/rxd2/smiso2/sscl2 seg06 41 p51 mtioc4c rspcka/sck2 seg07 42 p50 mtioc2a mosia/txd2/smosi2/ssda2 seg08 43 p55 mtioc4d/tmo3 vl1 44 p54 mtioc4b/tmci1 vl2 45 pc7 mtioc3a/mtclkb/ tmo2 txd1/smosi1/ssda1/misoa/ txd8/smosi8/ssda8/ usb0_ovrcurb vl3 cacref 46 pc6 mtioc3c/mtclka/ tmci2 rxd1/smiso1/sscl1/mosia/ rxd8/smiso8/sscl8/ usb0_exicen vl4 47 pc5 mtioc3b/mtclkd/ tmri2 sck1/rspcka/sck8/usb0_id com0 48 pc4 mtioc3d/mtclkc/ poe0#/tmci1 ssla0/cts8#/rts8#/ss8#/sck5/ usb0_vbusen/usb0_vbus * 1 com1 irq2/clkout 49 pc3 mtioc4d txd5/smosi5/ssds5/irtxd5 com2 50 pc2 mtioc4b rxd5/smosi5/sscl5/irrxd5/ ssla3 com3 51 pc1 mtioc3a sck5/ssla2 seg09 52 pc0 mtioc3c cts5#/rts5#/ss5#/ssla1 seg10 53 pb7 mtioc3b txd9/smosi9/ssda9/ssitxd0 seg11/ com4 54 pb6 mtioc3d rxd9/smiso9/sscl9/ssirxd0 seg12/ com5 55 pb5 mtioc1b/mtioc2a/ poe1#/tmri1 sck9/ssisck0 seg13/ com6 56 pb4 cts9#/rts9#/ss9# seg14 57 pb3 mtioc0a/mtioc3b/ mtioc4a/poe3#/tmo0 sck6/audio_mclk/ usb0_ovrcura seg15/ com7 58 pb2 cts6#/rts6#/ss6# seg16 59 pb1 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6/ssiws0 seg17 irq4 60 vcc 61 pb0 mtioc0c/mtic5w/ rtcout scl0/rspcka/rxd6/smiso6/ sscl6 irq2/adtrg0# 62 vss 63 pa6 mtic5v/mtclkb/ mtioc2a/poe2#/tmci3 cts5#/rts5#/ss5#/sda0/mosia/ rxd8/smiso8/sscl8 irq3 64 pa7 txd8/smosi8/ssds8 seg18 65 pa5 sck8 seg19 66 pa4 mtioc2b/mtic5u/ mtclka/tmri0 txd5/smosi5/ssda5/irtxd5/ ssla0/cts8#/rts8#/ss8# seg20 irq5/cvrefb1 67 pa3 mtioc0d/mtioc1b/ mtclkd/poe0# rxd5/smiso5/sscl5/irrxd5/ misoa seg21 irq6/cmpb1 table 1.5 list of pins and pin functions (100-pin lfqfp) (2/3) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others
r01ds0216ej0102 rev.1.02 page 18 of 121 dec 01, 2014 rx113 group 1. overview note 1. not 5 v tolerant. 68 pa2 rxd5/smiso5/sscl5/irrxd5/ ssla3 seg22 69 pa1 mtioc0b/mtclkc/ rtcout sck5/ssla2 seg23 70 pa0 mtioc4a ssla1 seg24 cacref 71 pf7 mtioc3a seg25 72 pf6 mtioc3c seg26 73 pe5 mtioc2b/mtioc4c misoa/txd9/smosi9/ssda9 seg27 irq5/an013/ cmpob1 74 pe4 mtioc1a/mtioc3a/ mtioc4d mosia/rxd9/smiso9/sscl9/ ssiws0 seg28 irq4/an012 75 pe3 mtioc0a/mtioc1b/ mtioc4b/poe8# cts12#/rts12#/ss12#/rspcka/ sck9/audio_mclk seg29 irq3/an011 76 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12/ssirxd0 seg30 irq7/an010/ cvrefb0 77 pe1 mtioc4c txd12/txdx12/siox12/smosi12/ ssda12/ssitxd0 seg31 irq1/an009/ cmpb0 78 pe0 mtioc2a/poe3# sck12/cts9#/rts9#/ss9#/ ssisck0 seg32 irq0/an008 79 pe7 seg33 irq7/an015/ cmpob0 80 pe6 seg34 irq6/an014 81 pd4 poe3# seg35 irq4 82 pd3 poe8# seg36 irq3 83 pd2 mtioc4d seg37 irq2 84 pd1 mtioc4b seg38 irq1 85 pd0 seg39 irq0 86 p92 an021 87 p91 an007 88 p46 an006 89 p90 an005 90 p44 an004 91 p43 an003 92 vrefl p42 an002 93 vrefh p41 an001 94 vrefl0 pj7 95 p40 an000 96 vrefh0 pj6 97 avss0 98 avcc0 99 p07 txd6/smosi6/ssda6 ts0 adtrg0# 100 pj2 da1 table 1.5 list of pins and pin functions (100-pin lfqfp) (3/3) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others
r01ds0216ej0102 rev.1.02 page 19 of 121 dec 01, 2014 rx113 group 1. overview table 1.6 list of pins and pin functions (100-pin tflga) (1/3) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others a1 p02 mtioc0d/poe3#/tmri3 rxd6/smiso6/sscl6 ts2 a2 p07 txd6/smosi6/ssda6 ts0 adtrg0# a3 avcc0 a4 avss0 a5 p44 an004 a6 p92 an021 a7 pd3 poe8# seg36 irq3 a8 pe6 seg34 irq6/an014 a9 pe7 seg33 irq7/an015/ cmpob0 a10 pe0 mtioc2a/poe3# sck12/cts9#/rts9#/ss9#/ ssisck0 seg32 irq0/an008 b1 p25 mtioc4c/mtclkb ts4 adtrg0# b2 p04 mtioc0a/poe2#/tmci3 sck6 ts1 b3 pj2 da1 b4 vrefl0 pj7 b5 p90 an005 b6 pd0 seg39 irq0 b7 pd4 poe3# seg35 irq4 b8 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12/ssirxd0 seg30 irq7/an010/ cvrefb0 b9 pe1 mtioc4c txd12/txdx12/siox12/smosi12/ ssda12/ssitxd0 seg31 irq1/an009/ cmpb0 b10 pe3 mtioc0a/mtioc1b/ mtioc4b/poe8# cts12#/rts12#/ss12#/rspcka/ sck9/audio_mclk seg29 irq3/an011 c1 pj3 mtioc3c cts6#/rts6#/ss6# ts3 c2 p24 mtioc4a/mtclka/ tmri1 ts5 c3 vrefh0 pj6 c4 vrefh p41 an001 c5 vrefl p42 an002 c6 p91 an007 c7 pd1 mtioc4b seg38 irq1 c8 pd2 mtioc4d seg37 irq2 c9 pe5 mtioc2b/mtioc4c misoa/txd9/smosi9/ssda9 seg27 irq5/an013/ cmpob1 c10 pe4 mtioc1a/mtioc3a/ mtioc4d mosia/rxd9/smiso9/sscl9/ ssiws0 seg28 irq4/an012 d1 p22 mtioc3b/mtclkc/ tmo0 sck0 ts7 d2 p23 mtioc3d/mtclkd cts0#/rts0#/ss0# ts6 d3 p21 mtioc1b/tmci0 rxd0/smiso0/sscl0 ts8 d4 pj0 da0 d5 p43 an003 d6 p46 an006 d7 pf6 mtioc3c seg26 d8 pf7 mtioc3a seg25
r01ds0216ej0102 rev.1.02 page 20 of 121 dec 01, 2014 rx113 group 1. overview d9 pa1 mtioc0b/mtclkc/ rtcout sck5/ssla2 seg23 d10 pa0 mtioc4a ssla1 seg24 cacref e1 p30 mtioc4b/poe8#/tmri3 rxd1/smiso1/sscl1 caph irq0 e2 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# capl irq1 e3 p26 mtioc2a/tmo1 txd1/smosi1/ssda1/ usb0_vbusen/txd6/smosi6/ ssda6 tscap e4 p20 mtioc1a/tmri0 txd0/smosi0/ssda0 ts9 e5 p40 an000 e6 pa2 rxd5/smiso5/sscl5/irrxd5/ ssla3 seg22 e7 pa4 mtioc2b/mtic5u/ mtclka/tmri0 txd5/smosi5/ssda5/irtxd5/ ssla0/cts8#/rts8#/ss8# seg20 irq5/cvrefb1 e8 pa5 sck8 seg19 e9 pa3 mtioc0d/mtioc1b/ mtclkd/poe0# rxd5/smiso5/sscl5/irrxd5/ misoa seg21 irq6/cmpb1 e10 vss f1 xcout f2 upsel p35 nmi f3 res# f4 p27 mtioc2b/tmci3 sck12/sck1/rxd6/smiso6/ sscl6 ts10 irq3/ adtrg0#/ cacref/ cmpa2 f5 p56 mtioc1a/mtic5w/ poe2# txd1/smosi1/ssda1 seg4 irq5 f6 pb4 cts9#/rts9#/ss9# seg14 f7 pa7 txd8/smosi8/ssds8 seg18 f8 pb0 mtioc0c/mtic5w/ rtcout scl0/rspcka/rxd6/smiso6/ sscl6 irq2/adtrg0# f9 pa6 mtic5v/mtclkb/ mtioc2a/poe2#/tmci3 cts5#/rts5#/ss5#/sda0/mosia/ rxd8/smiso8/sscl8 irq3 f10 vcc g1 xcin ph7 g2 ub# p14 mtioc0a/mtioc3a/ mtclka/tmri2 cts1#/rts1#/ss1#/ssla0/ txd12/txdx12/siox12/smosi12/ ssda12/usb0_ovrcura irq4 g3 p12 tmci1 sck12/sck0 seg01 irq2 g4 md fined g5 p10 mtic5v/poe1# txd12/txdx12/siox12/smosi12/ ssda12/txd0/smosi0/ssda0 seg03 irq6 g6 p50 mtioc2a mosia/txd2/smosi2/ssda2 seg08 g7 pb5 mtioc1b/mtioc2a/ poe1#/tmri1 sck9/ssisck0 seg13/ com6 g8 pb2 cts6#/rts6#/ss6# seg16 g9 pb1 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6/ssiws0 seg17 irq4 g10 pb3 mtioc0a/mtioc3b/ mtioc4a/poe3#/tmo0 sck6/audio_mclk/ usb0_ovrcura seg15/ com7 table 1.6 list of pins and pin functions (100-pin tflga) (2/3) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others
r01ds0216ej0102 rev.1.02 page 21 of 121 dec 01, 2014 rx113 group 1. overview note 1. not 5 v tolerant. h1 xtal h2 extal h3 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1/rspcka irq5/clkout/ cacref h4 p13 mtioc0b/tmo3 cts12#/rts12#/ss12#/cts0#/ rts0#/ss0# seg00 irq3 h5 p11 mtic5u/poe0# rxd12/rxdx12/smiso12/ sscl12/rxd0/smiso0/sscl0 seg02 irq7 h6 p51 mtioc4c rspcka/sck2 seg07 h7 pc0 mtioc3c cts5#/rts5#/ss5#/ssla1 seg10 h8 pc1 mtioc3a sck5/ssla2 seg09 h9 pb6 mtioc3d rxd9/smiso9/sscl9/ssirxd0 seg12/ com5 h10 pb7 mtioc3b txd9/smosi9/ssda9/ssitxd0 seg11/ com4 j1 vcl j2 p17 mtioc0c/mtioc3a/ mtioc3b/poe8#/tmo1 sck1/misoa/sda0/rxd12/ rxdx12/smiso12/sscl12 irq7 j3 p32 mtioc0c/rtcout/ tmo3 txd6/smosi6/ssda6/cts6#/ rts6#/ss6# ts11 irq2 j4 vcc_usb j5 vss_usb j6 p52 misoa/rxd2/smiso2/sscl2 seg06 j7 p55 mtioc4d/tmo3 vl1 j8 pc7 mtioc3a/mtclkb/ tmo2 txd1/smosi1/ssda1/misoa/ txd8/smosi8/ssda8/ usb0_ovrcurb vl3 cacref j9 pc4 mtioc3d/mtclkc/ poe0#/tmci1 ssla0/cts8#/rts8#/ss8#/sck5/ usb0_vbusen/usb0_vbus * 1 com1 irq2/clkout j10 pc2 mtioc4b rxd5/smosi5/sscl5/irrxd5/ ssla3 com3 k1 vss k2 vdd k3 p16 mtioc3c/mtioc3d/ rtcout/tmo2 txd1/smosi1/ssda1/mosia/ scl0/usb0_vbus/ usb0_vbusen/usb0_ovrcurb irq6/adtrg0# k4 usb0_dm k5 usb0_dp k6 p53 mtioc2b ssla0/cts2#/rts2#/ss2# seg05 k7 p54 mtioc4b/tmci1 vl2 k8 pc6 mtioc3c/mtclka/ tmci2 rxd1/smiso1/sscl1/mosia/ rxd8/smiso8/sscl8/ usb0_exicen vl4 k9 pc5 mtioc3b/mtclkd/ tmri2 sck1/rspcka/sck8/usb0_id com0 k10 pc3 mtioc4d txd5/smosi5/ssds5/irtxd5 com2 table 1.6 list of pins and pin functions (100-pin tflga) (3/3) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others
r01ds0216ej0102 rev.1.02 page 22 of 121 dec 01, 2014 rx113 group 1. overview table 1.7 list of pins and pin functions (64-pin lfqfp) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others 1p j 0 da0 2 p27 mtioc2b/tmci3 sck1/sck12/rxd6/smiso6/ sscl6 irq3/cmpa2/ cacref/ adtrg0# 3 p26 mtioc2a/tmo1 txd1/smosi1/ssda1/ usb0_vbusen/txd6/smosi6/ ssda6 4 p30 mtioc4b/poe8#/tmri3 rxd1/smiso1/sscl1 caph irq0 5 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# capl irq1 6md fined 7res# 8xcout 9xcin ph7 10 upsel p35 nmi 11 xtal 12 extal 13 vcl 14 vss 15 vcc 16 p32 mtioc0c/rtcout/ tmo3 txd6/smosi6/ssda6/cts6#/ rts6#/ss6# irq2 17 p17 mtioc0c/mtioc3a/ mtioc3b/poe8#/tmo1 sck1/misoa/sda0/rxd12/ rxdx12/smiso12/sscl12 irq7 18 p16 mtioc3c/mtioc3d/ rtcout/tmo2 txd1/smosi1/ssda1/mosia/ scl0/usb0_vbus/ usb0_vbusen/usb0_ovrcurb irq6/adtrg0# 19 p15 mtioc0b/mtclkb/ tmci2 rxd1/smiso1/sscl1/rspcka irq5/clkout/ cacref 20 ub# p14 mtioc0a/mtioc3a/ mtclka/tmri2 cts1#/rts1#/ss1#/ssla0/ txd12/txdx12/siox12/smosi12/ ssda12/usb0_ovrcura irq4 21 vcc_usb 22 usb0_dm 23 usb0_dp 24 vss_usb 25 p55 mtioc4d/tmo3 vl1 26 p54 mtioc4b/tmci1 vl2 27 pc7 mtioc3a/mtclkb/ tmo2 txd1/smosi1/ssda1/misoa/ txd8/smosi8/ssda8/ usb0_ovrcurb vl3 cacref 28 pc6 mtioc3c/mtclka/ tmci2 rxd1/smiso1/sscl1/mosia/ rxd8/smiso8/sscl8/ usb0_exicen vl4 29 pc5 mtioc3b/mtclkd/ tmri2 sck1/rspcka/sck8/usb0_id com0 30 pc4 mtioc3d/mtclkc/ poe0#/tmci1 ssla0/cts8#/rts8#/ss8#/sck5/ usb0_vbusen/usb0_vbus * 1 com1 irq2/clkout 31 pc3 mtioc4d txd5/smosi5/ssda5/irtxd5 com2 32 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3/ irrxd5 com3
r01ds0216ej0102 rev.1.02 page 23 of 121 dec 01, 2014 rx113 group 1. overview note 1. not 5 v tolerant. 33 pb7/ pc1 mtioc3b txd9/smosi9/ssda9/ssitxd0 seg11/ com4 34 pb6/ pc0 mtioc3d rxd9/smosi9/sscl9/ssirxd0 seg12/ com5 35 pb5 mtioc2a/mtioc1b/ poe1#/tmri1 sck9/ssisck0 seg13/ com6 36 pb3 mtioc0a/mtioc3b/ mtioc4a/poe3#/tmo0 sck6/audio_mclk/ usb0_ovrcura seg15/ com7 37 pb1 mtioc0c/mtioc4c/ tmci0 txd6/smosi6/ssda6/ssiws0 seg17 irq4 38 vcc 39 pb0 mtic5w/mtioc0c/ rtcout scl0/rspcka/rxd6/smosi6/ sscl6 irq2/adtrg0# 40 vss 41 pa6 mtic5v/mtclkb/ mtioc2a/poe2#/tmci3 cts5#/rts5#/ss5#/sda0/mosia irq3 42 pa4 mtic5u/mtclka/ mtioc2b/tmri0 txd5/smosi5/ssda5/irtxd5/ ssla0 seg20 irq5/cvrefb1 43 pa3 mtioc0d/mtclkd/ mtioc1b/poe0# rxd5/smiso5/sscl5/irrxd5/ misoa seg21 irq6/cmpb1 44 pa1 mtioc0b/mtclkc/ rtcout sck5/ssla2 seg23 45 pa0 mtioc4a ssla1 seg24 cacref 46 pe5 mtioc4c/mtioc2b misoa/txd9/smosi9/ssda9 seg27 irq5/an013/ cmpob1 47 pe4 mtioc4d/mtioc1a/ mtioc3a mosia/rxd9/smiso9/sscl9/ ssiws0 seg28 irq4/an012 48 pe3 mtioc0a/mtioc1b/ mtioc4b/poe8# cts12#/rts12#/ss12#/rspcka/ sck9/audio_mclk seg29 irq3/an011 49 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12/rxdx12/ssirxd0 seg30 irq7/an010/ cvrefb0 50 pe1 mtioc4c txd12/txdx12/siox12/smosi12/ ssda12/ssitxd0 seg31 irq1/an009/ cmpb0 51 pe0 mtioc2a/poe3# sck12/cts9#/rts9#/ss6#/ ssisck0 seg32 irq0/an008 52 pe7 seg33 irq7/an015/ cmpob0 53 pe6 seg34 irq6/an014 54 pd2 mtioc4d seg37 irq2 55 pd1 mtioc4b seg38 irq1 56 pd0 seg39 irq0 57 vrefl p42 an002 58 vrefh p41 an001 59 vrefl0 pj7 60 p40 an000 61 vrefh0 pj6 62 avss0 63 avcc0 64 pj2 da1 table 1.7 list of pins and pin functions (64-pin lfqfp) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, poe, rtc, tmr) communication (scie, scif, rspi, riic, usb, ssi) lcd, touch others
r01ds0216ej0102 rev.1.02 page 24 of 121 dec 01, 2014 rx113 group 2. cpu 2. cpu figure 2.1 shows the register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack poi nter (isp) or user stack pointer (usp), according to the value of the u bit in the psw register. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose registers control registers b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0216ej0102 rev.1.02 page 25 of 121 dec 01, 2014 rx113 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has 16 general-purpose registers (r 0 to r15). r0 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of 4, as this reduces the nu mbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. 2.3 register associated with dsp instructions (1) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate inst ructions; emul, emulu, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0216ej0102 rev.1.02 page 26 of 121 dec 01, 2014 rx113 group 3. address space 3. address space 3.1 address space this mcu has a 4-gbyte address space, consisting of the range of addresses from 0000 0000h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is possible, and this contains program area. figure 3.1 shows the memory map.
r01ds0216ej0102 rev.1.02 page 27 of 121 dec 01, 2014 rx113 group 3. address space figure 3.1 memory map reserved area* 3 reserved area* 3 reserved area* 3 on-chip rom (e2 dataflash) (8 kb) reserved area* 3 single-chip mode* 1 ram* 2 on-chip rom (program rom)* 2 peripheral i/o registers peripheral i/o registers peripheral i/o registers 0000 0000h 0001 0000h 0008 0000h 0010 0000h 0010 2000h 007f c000h 007f c500h 007f fc00h 0080 0000h fff8 0000h ffff ffffh note 1. the address space in boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note: see table 1.3, list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) capacity address capacity address 512 k fff8 0000h to ffff ffffh 64 k 0000 0000h to 0000 ffffh 384 k fffa 0000h to ffff ffffh 256 k fffc 0000h to ffff ffffh 32 k 0000 0000h to 0000 7fffh 128 k fffe 0000h to ffff ffffh
r01ds0216ej0102 rev.1.02 page 28 of 121 dec 01, 2014 rx113 group 4. i/o registers 4. i/o registers this section provides information on the on-chip i/o register addresses and bit configuration. the information is given as shown below. notes on writing to i/o registers are also given below. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers while writing to an i/o register, the cpu starts execu ting subsequent instructions before the i/o register write access is completed. this may cause the subsequent instructions to be executed before the write value is reflected in the operation. the examples below show how subsequent instructions must be executed after a write access to an i/o register is completed. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request enable bit) set to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value in the i/o register and write it to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. example of instructions ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0216ej0102 rev.1.02 page 29 of 121 dec 01, 2014 rx113 group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process when executing an instruction after writing to multiple registers, only read the last i/o register written to and execute the instruction using that value; it is not necessary to execute the instruction using the values written to all the registers. (3) number of cycles necessary for accessing i/o registers see table 4.1 for details on the number of clock cycl es necessary for accessing i/o registers. the number of access cycles to i/o regist ers is obtained by following equation. *1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral buses 1 to 6 the number of bus cycles of internal peripheral buses 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral buses 2 to 6 or registers for the external bus control unit (except for bus error related registers) are accessed, the number of divided cl ock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. note 1. this applies to the number of cycles when the access fr om the cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dtc). (4) notes on sleep mode and mode transitions during sleep mode or mode transitions, do not write to the sy stem control related registers (indicated by ?system? in the module symbol column in table 4.1, list of i/o registers (address order) ).
r01ds0216ej0102 rev.1.02 page 30 of 121 dec 01, 2014 rx113 group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o regist ers (address order) (1/23) address module symbol register name register symbol number of bits access size number of access states 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 001ch system module stop control register d mstpcrd 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 002ch system usb-dedicated pll control register upllcr 16 16 3iclk 0008 002eh system usb-dedicated pll control register 2 upllcr2 8 8 3iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0033h system sub-clock oscillator control register sosccr 8 8 3 iclk 0008 0034h system low-speed on-chip oscillator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0036h system high-speed on-chip osc illator control register hococr 8 8 3 iclk 0008 003ch system oscillation stabilization flag register oscovfsr 8 8 3 iclk 0008 003eh system clkout output control register ckocr 16 16 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 0050h system lcd source clock control register lcdsclkcr 8 8 3 iclk 0008 0051h system lcd source clock control register 2 lcdsclkcr2 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a1h system sleep mode return clock source switching register rstckcr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register moscwtcr 8 8 3 iclk 0008 00a5h system high-speed on-chip oscillat or wait control register hocowtcr 8 8 3 iclk 0008 00aah system sub operating power control register sopccr 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk
r01ds0216ej0102 rev.1.02 page 31 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 7024h icu interrupt request register 036 ir036 8 8 2 iclk 0008 7025h icu interrupt request register 037 ir037 8 8 2 iclk 0008 7026h icu interrupt request register 038 ir038 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk 0008 703ah icu interrupt request register 058 ir058 8 8 2 iclk 0008 703bh icu interrupt request register 059 ir059 8 8 2 iclk 0008 703ch icu interrupt request register 060 ir060 8 8 2 iclk 0008 703dh icu interrupt request register 061 ir061 8 8 2 iclk 0008 703eh icu interrupt request register 062 ir062 8 8 2 iclk 0008 703fh icu interrupt request register 063 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 705ah icu interrupt request register 090 ir090 8 8 2 iclk 0008 705ch icu interrupt request register 092 ir092 8 8 2 iclk 0008 705dh icu interrupt request register 093 ir093 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 706ch icu interrupt request register 108 ir108 8 8 2 iclk 0008 706dh icu interrupt request register 109 ir109 8 8 2 iclk 0008 706eh icu interrupt request register 110 ir110 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (2/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 32 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70bh6 icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70bah icu interrupt request register 186 ir186 8 8 2 iclk 0008 70bbh icu interrupt request register 187 ir187 8 8 2 iclk 0008 70bch icu interrupt request register 188 ir188 8 8 2 iclk 0008 70bdh icu interrupt request register 189 ir189 8 8 2 iclk 0008 70d6h icu interrupt request register 214 ir214 8 8 2 iclk 0008 70d7h icu interrupt request register 215 ir215 8 8 2 iclk 0008 70d8h icu interrupt request register 216 ir216 8 8 2 iclk 0008 70d9h icu interrupt request register 217 ir217 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70e6h icu interrupt request register 230 ir230 8 8 2 iclk 0008 70e7h icu interrupt request register 231 ir231 8 8 2 iclk 0008 70e8h icu interrupt request register 232 ir232 8 8 2 iclk 0008 70e9h icu interrupt request register 233 ir233 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (3/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 33 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 7124h icu dtc activation enable register 036 dtcer036 8 8 2 iclk 0008 7125h icu dtc activation enable register 037 dtcer037 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 713ah icu dtc activation enable register 058 dtcer058 8 8 2 iclk 0008 713bh icu dtc activation enable register 059 dtcer059 8 8 2 iclk 0008 713ch icu dtc activation enable register 060 dtcer060 8 8 2 iclk 0008 713dh icu dtc activation enable register 061 dtcer061 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 716ah icu dtc activation enable register 106 dtcer106 8 8 2 iclk 0008 716dh icu dtc activation enable register 109 dtcer109 8 8 2 iclk 0008 716eh icu dtc activation enable register 110 dtcer110 8 8 2 iclk 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (4/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 34 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71bbh icu dtc activation enable register 187 dtcer187 8 8 2 iclk 0008 71bch icu dtc activation enable register 188 dtcer188 8 8 2 iclk 0008 71d7h icu dtc activation enable register 215 dtcer215 8 8 2 iclk 0008 71d8h icu dtc activation enable register 216 dtcer216 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71e7h icu dtc activation enable register 231 dtcer231 8 8 2 iclk 0008 71e8h icu dtc activation enable register 232 dtcer232 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (5/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 35 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 721ah icu interrupt request enable register 1a ier1a 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk 0008 7324h icu interrupt source priority register 036 ipr036 8 8 2 iclk 0008 7325h icu interrupt source priority register 037 ipr037 8 8 2 iclk 0008 7326h icu interrupt source priority register 038 ipr038 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 733ah icu interrupt source priority register 058 ipr058 8 8 2 iclk 0008 733bh icu interrupt source priority register 059 ipr059 8 8 2 iclk 0008 733ch icu interrupt source priority register 060 ipr060 8 8 2 iclk 0008 733fh icu interrupt source priority register 063 ipr063 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 iclk 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 iclk 0008 7358h icu interrupt source priority register 088 ipr088 8 8 2 iclk 0008 7359h icu interrupt source priority register 089 ipr089 8 8 2 iclk 0008 735ah icu interrupt source priority register 090 ipr090 8 8 2 iclk 0008 735ch icu interrupt source priority register 092 ipr092 8 8 2 iclk 0008 735dh icu interrupt source priority register 093 ipr093 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 iclk 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 iclk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 iclk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 iclk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 iclk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 iclk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 iclk 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 iclk table 4.1 list of i/o regist ers (address order) (6/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 36 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk 0008 73aah icu interrupt source priority register 170 ipr170 8 8 2 iclk 0008 73abh icu interrupt source priority register 171 ipr171 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk 0008 73bah icu interrupt source priority register 186 ipr186 8 8 2 iclk 0008 73d6h icu interrupt source priority register 214 ipr214 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 iclk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 iclk 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 iclk 0008 73e6h icu interrupt source priority register 230 ipr230 8 8 2 iclk 0008 73eah icu interrupt source priority register 234 ipr234 8 8 2 iclk 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 2 iclk 0008 73f2h icu interrupt source priority register 242 ipr242 8 8 2 iclk 0008 73f3h icu interrupt source priority register 243 ipr243 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 2 iclk 0008 73f5h icu interrupt source priority register 245 ipr245 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 iclk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 or 3 pclkb 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2 or 3 pclkb 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2 or 3 pclkb 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2 or 3 pclkb 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2 or 3 pclkb 0008 8010h cmt compare match timer start register1 cmstr1 16 16 2 or 3 pclkb 0008 8012h cmt2 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8014h cmt2 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 8016h cmt2 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8018h cmt3 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 801ah cmt3 compare match counter cmcnt 16 16 2 or 3 pclkb table 4.1 list of i/o regist ers (address order) (7/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 37 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 801ch cmt3 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 or 3 pclkb 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 or 3 pclkb 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 or 3 pclkb 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2 or 3 pclkb 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2 or 3 pclkb 0008 8040h r12da d/a data register 0 dadr0 16 16 2 or 3 pclkb 0008 8042h r12da d/a data register 1 dadr1 16 16 2 or 3 pclkb 0008 8044h r12da d/a control register dacr 8 8 2 or 3 pclkb 0008 8045h r12da dadrm format select register dadpr 8 8 2 or 3 pclkb 0008 8046h r12da d/a a/d synchronous start control register daadscr 8 8 2 or 3 pclkb 0008 8047h r12da d/a vref control register davrefcr 8 8 2 or 3 pclkb 0008 8200h tmr0 timer control register tcr 8 8 2 or 3 pclkb 0008 8201h tmr1 timer control register tcr 8 8 2 or 3 pclkb 0008 8202h tmr0 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8203h tmr1 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8204h tmr0 time constant register a tcora 8 8 2 or 3 pclkb 0008 8205h tmr1 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8206h tmr0 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8208h tmr0 timer counter tcnt 8 8 2 or 3 pclkb 0008 8209h tmr1 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 820ah tmr0 timer counter control register tccr 8 8 2 or 3 pclkb 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 820ch tmr0 time count start register tcstr 8 8 2 or 3 pclkb 0008 8210h tmr2 timer control register tcr 8 8 2 or 3 pclkb 0008 8211h tmr3 timer control register tcr 8 8 2 or 3 pclkb 0008 8212h tmr2 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8213h tmr3 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8214h tmr2 time constant register a tcora 8 8 2 or 3 pclkb 0008 8215h tmr3 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8216h tmr2 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8218h tmr2 timer counter tcnt 8 8 2 or 3 pclkb 0008 8219h tmr3 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 821ah tmr2 timer control register tccr 8 8 2 or 3 pclkb 0008 821bh tmr3 timer control register tccr 8 8* 1 2 or 3 pclkb 0008 821ch tmr2 time count start register tcstr 8 8 2 or 3 pclkb 0008 8280h crc crc control register crccr 8 8 2 or 3 pclkb 0008 8281h crc crc data input register crcdir 8 8 2 or 3 pclkb 0008 8282h crc crc data output register crcdor 16 16 2 or 3 pclkb 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2 or 3 pclkb 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2 or 3 pclkb 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2 or 3 pclkb 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2 or 3 pclkb 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2 or 3 pclkb 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2 or 3 pclkb 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2 or 3 pclkb 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2 or 3 pclkb 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2 or 3 pclkb 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2 or 3 pclkb 0008 830ah riic0 slave address register l0 sarl0 8 8 2 or 3 pclkb table 4.1 list of i/o regist ers (address order) (8/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 38 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 830ah riic0 timeout internal counter l tmocntl 8 8 2 or 3 pclkb 0008 830bh riic0 slave address register u0 saru0 8 8 2 or 3 pclkb 0008 830bh riic0 timeout internal counter u tmocntu 8 8 * 2 2 or 3 pclkb 0008 830ch riic0 slave address register l1 sarl1 8 8 2 or 3 pclkb 0008 830dh riic0 slave address register u1 saru1 8 8 2 or 3 pclkb 0008 830eh riic0 slave address register l2 sarl2 8 8 2 or 3 pclkb 0008 830fh riic0 slave address register u2 saru2 8 8 2 or 3 pclkb 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2 or 3 pclkb 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2 or 3 pclkb 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2 or 3 pclkb 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2 or 3 pclkb 0008 8380h rspi0 rspi control register spcr 8 8 2 or 3 pclkb 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 or 3 pclkb 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 or 3 pclkb 0008 8383h rspi0 rspi status register spsr 8 8 2 or 3 pclkb 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 or 3 pclkb/2iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 or 3 pclkb 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 or 3 pclkb 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 or 3 pclkb 0008 838bh rspi0 rspi data control register spdcr 8 8 2 or 3 pclkb 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 or 3 pclkb 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 or 3 pclkb 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 or 3 pclkb 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 or 3 pclkb 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 or 3 pclkb 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 or 3 pclkb 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 or 3 pclkb 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 or 3 pclkb 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 or 3 pclkb 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 or 3 pclkb 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 or 3 pclkb 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 or 3 pclkb 0008 8410h irda irda control register ircr 8 8 2 or 3 pclkb 0008 8600h mtu3 timer control register tcr 8 8 2 or 3 pclkb 0008 8601h mtu4 timer control register tcr 8 8 2 or 3 pclkb 0008 8602h mtu3 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8603h mtu4 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2 or 3 pclkb 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2 or 3 pclkb 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2 or 3 pclkb 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2 or 3 pclkb 0008 8608h mtu3 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8609h mtu4 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 860ah mtu timer output master enable register toer 8 8 2 or 3 pclkb 0008 860dh mtu timer gate control register tgcr 8 8 2 or 3 pclkb 0008 860eh mtu timer output control register 1 tocr1 8 8 2 or 3 pclkb 0008 860fh mtu timer output control register 2 tocr2 8 8 2 or 3 pclkb 0008 8610h mtu3 timer counter tcnt 16 16 2 or 3 pclkb 0008 8612h mtu4 timer counter tcnt 16 16 2 or 3 pclkb 0008 8614h mtu timer cycle data register tcdr 16 16 2 or 3 pclkb 0008 8616h mtu timer dead time data register tddr 16 16 2 or 3 pclkb 0008 8618h mtu3 timer general register a tgra 16 16 2 or 3 pclkb table 4.1 list of i/o regist ers (address order) (9/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 39 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 861ah mtu3 timer general register b tgrb 16 16 2 or 3 pclkb 0008 861ch mtu4 timer general register a tgra 16 16 2 or 3 pclkb 0008 861eh mtu4 timer general register b tgrb 16 16 2 or 3 pclkb 0008 8620h mtu timer subcounter tcnts 16 16 2 or 3 pclkb 0008 8622h mtu timer cycle buffer register tcbr 16 16 2 or 3 pclkb 0008 8624h mtu3 timer general register c tgrc 16 16 2 or 3 pclkb 0008 8626h mtu3 timer general register d tgrd 16 16 2 or 3 pclkb 0008 8628h mtu4 timer general register c tgrc 16 16 2 or 3 pclkb 0008 862ah mtu4 timer general register d tgrd 16 16 2 or 3 pclkb 0008 862ch mtu3 timer status register tsr 8 8 2 or 3 pclkb 0008 862dh mtu4 timer status register tsr 8 8 2 or 3 pclkb 0008 8630h mtu timer interrupt skipping set register titcr 8 8 2 or 3 pclkb 0008 8631h mtu timer interrupt skipping counter titcnt 8 8 2 or 3 pclkb 0008 8632h mtu timer buffer transfer set register tbter 8 8 2 or 3 pclkb 0008 8634h mtu timer dead time enable register tder 8 8 2 or 3 pclkb 0008 8636h mtu timer output level buffer register tolbr 8 8 2 or 3 pclkb 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2 or 3 pclkb 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2 or 3 pclkb 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2 or 3 pclkb 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2 or 3 pclkb 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2 or 3 pclkb 0008 8660h mtu timer waveform control register twcr 8 8, 16 2 or 3 pclkb 0008 8680h mtu timer start register tstr 8 8, 16 2 or 3 pclkb 0008 8681h mtu timer synchronous register tsyr 8 8, 16 2 or 3 pclkb 0008 8684h mtu timer read/write enable register trwer 8 8, 16 2 or 3 pclkb 0008 8690h mtu0 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8691h mtu1 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8692h mtu2 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8693h mtu3 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8694h mtu4 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8695h mtu5 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8700h mtu0 timer control register tcr 8 8 2 or 3 pclkb 0008 8701h mtu0 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2 or 3 pclkb 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2 or 3 pclkb 0008 8704h mtu0 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8705h mtu0 timer status register tsr 8 8 2 or 3 pclkb 0008 8706h mtu0 timer counter tcnt 16 16 2 or 3 pclkb 0008 8708h mtu0 timer general register a tgra 16 16 2 or 3 pclkb 0008 870ah mtu0 timer general register b tgrb 16 16 2 or 3 pclkb 0008 870ch mtu0 timer general register c tgrc 16 16 2 or 3 pclkb 0008 870eh mtu0 timer general register d tgrd 16 16 2 or 3 pclkb 0008 8720h mtu0 timer general register e tgre 16 16 2 or 3 pclkb 0008 8722h mtu0 timer general register f tgrf 16 16 2 or 3 pclkb 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2 or 3 pclkb 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 0008 8780h mtu1 timer control register tcr 8 8 2 or 3 pclkb 0008 8781h mtu1 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8782h mtu1 timer i/o control register tior 8 8 2 or 3 pclkb 0008 8784h mtu1 timer interrupt enable register tier 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (10/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 40 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 8785h mtu1 timer status register tsr 8 8 2 or 3 pclkb 0008 8786h mtu1 timer counter tcnt 16 16 2 or 3 pclkb 0008 8788h mtu1 timer general register a tgra 16 16 2 or 3 pclkb 0008 878ah mtu1 timer general register b tgrb 16 16 2 or 3 pclkb 0008 8790h mtu1 timer input capture control register ticcr 8 8 2 or 3 pclkb 0008 8800h mtu2 timer control register tcr 8 8 2 or 3 pclkb 0008 8801h mtu2 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8802h mtu2 timer i/o control register tior 8 8 2 or 3 pclkb 0008 8804h mtu2 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8805h mtu2 timer status register tsr 8 8 2 or 3 pclkb 0008 8806h mtu2 timer counter tcnt 16 16 2 or 3 pclkb 0008 8808h mtu2 timer general register a tgra 16 16 2 or 3 pclkb 0008 880ah mtu2 timer general register b tgrb 16 16 2 or 3 pclkb 0008 8880h mtu5 timer counter u tcntu 16 16 2 or 3 pclkb 0008 8882h mtu5 timer general register u tgru 16 16 2 or 3 pclkb 0008 8884h mtu5 timer control register u tcru 8 8 2 or 3 pclkb 0008 8886h mtu5 timer i/o control register u tioru 8 8 2 or 3 pclkb 0008 8890h mtu5 timer counter v tcntv 16 16 2 or 3 pclkb 0008 8892h mtu5 timer general register v tgrv 16 16 2 or 3 pclkb 0008 8894h mtu5 timer control register v tcrv 8 8 2 or 3 pclkb 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2 or 3 pclkb 0008 88a0h mtu5 timer counter w tcntw 16 16 2 or 3 pclkb 0008 88a2h mtu5 timer general register w tgrw 16 16 2 or 3 pclkb 0008 88a4h mtu5 timer control register w tcrw 8 8 2 or 3 pclkb 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2 or 3 pclkb 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 88b4h mtu5 timer start register tstr 8 8 2 or 3 pclkb 0008 88b6h mtu5 timer compare match clear register tcntcmpclr 8 8 2 or 3 pclkb 0008 8900h poe input level control/status register 1 icsr1 16 8, 16 2 or 3 pclkb 0008 8902h poe output level control/status register 1 ocsr1 16 8, 16 2 or 3 pclkb 0008 8908h poe input level control/status register 2 icsr2 16 8, 16 2 or 3 pclkb 0008 890ah poe software port output enable register spoer 8 8 2 or 3 pclkb 0008 890bh poe port output enable control register 1 poecr1 8 8 2 or 3 pclkb 0008 890ch poe port output enable control register 2 poecr2 8 8 2 or 3 pclkb 0008 890eh poe input level control/status register 3 icsr3 16 8, 16 2 or 3 pclkb 0008 9000h s12ad a/d control register adcsr 16 16 2 or 3 pclkb 0008 9004h s12ad a/d channel select register a adansa 16 16 2 or 3 pclkb 0008 9006h s12ad a/d channel select register a1 adansa1 16 16 2 or 3 pclkb 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2 or 3 pclkb 0008 900ah s12ad a/d-converted value addition mode select register 1 adads1 16 16 2 or 3 pclkb 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2 or 3 pclkb 0008 900eh s12ad a/d control extended register adcer 16 16 2 or 3 pclkb 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2 or 3 pclkb 0008 9012h s12ad a/d converted extended input control register adexicr 16 16 2 or 3 pclkb 0008 9014h s12ad a/d channel select register b adansb 16 16 2 or 3 pclkb 0008 9016h s12ad a/d channel select register b1 adansb1 16 16 2 or 3 pclkb 0008 9018h s12ad a/d data duplication register addbldr 16 16 2 or 3 pclkb 0008 901ah s12ad a/d temperature sensor data register adtsdr 16 16 2 or 3 pclkb 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2 or 3 pclkb 0008 9020h s12ad a/d data register 0 addr0 16 16 2 or 3 pclkb 0008 9022h s12ad a/d data register 1 addr1 16 16 2 or 3 pclkb 0008 9024h s12ad a/d data register 2 addr2 16 16 2 or 3 pclkb table 4.1 list of i/o registers (address order) (11/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 41 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 9026h s12ad a/d data register 3 addr3 16 16 2 or 3 pclkb 0008 9028h s12ad a/d data register 4 addr4 16 16 2 or 3 pclkb 0008 902ah s12ad a/d data register 5 addr5 16 16 2 or 3 pclkb 0008 902ch s12ad a/d data register 6 addr6 16 16 2 or 3 pclkb 0008 902eh s12ad a/d data register 7 addr7 16 16 2 or 3 pclkb 0008 9030h s12ad a/d data register 8 addr8 16 16 2 or 3 pclkb 0008 9032h s12ad a/d data register 9 addr9 16 16 2 or 3 pclkb 0008 9034h s12ad a/d data register 10 addr10 16 16 2 or 3 pclkb 0008 9036h s12ad a/d data register 11 addr11 16 16 2 or 3 pclkb 0008 9038h s12ad a/d data register 12 addr12 16 16 2 or 3 pclkb 0008 903ah s12ad a/d data register 13 addr13 16 16 2 or 3 pclkb 0008 903ch s12ad a/d data register 14 addr14 16 16 2 or 3 pclkb 0008 903eh s12ad a/d data register 15 addr15 16 16 2 or 3 pclkb 0008 904ah s12ad a/d data register 21 addr21 16 16 2 or 3 pclkb 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2 or 3 pclkb 0008 9061h s12ad a/d sampling state register l adsstrl 8 8 2 or 3 pclkb 0008 9070h s12ad a/d sampling state register t adsstrt 8 8 2 or 3 pclkb 0008 9071h s12ad a/d sampling state register o adsstro 8 8 2 or 3 pclkb 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2 or 3 pclkb 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2 or 3 pclkb 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2 or 3 pclkb 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2 or 3 pclkb 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2 or 3 pclkb 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2 or 3 pclkb 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2 or 3 pclkb 0008 907ch s12ad a/d high-side reference voltage control register adhvrefcnt 8 8 2 or 3 pclkb 0008 9080h s12ad a/d sampling state register 21 adsstr21 8 8 2 or 3 pclkb 0008 a000h sci0 serial mode register smr 8 8 2 or 3 pclkb 0008 a001h sci0 bit rate register brr 8 8 2 or 3 pclkb 0008 a002h sci0 serial control register scr 8 8 2 or 3 pclkb 0008 a003h sci0 transmit data register tdr 8 8 2 or 3 pclkb 0008 a004h sci0 serial status register ssr 8 8 2 or 3 pclkb 0008 a005h sci0 receive data register rdr 8 8 2 or 3 pclkb 0008 a006h sci0 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a007h sci0 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a008h sci0 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a009h sci0 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a00ah sci0 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a00bh sci0 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a00ch sci0 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a00dh sci0 spi mode register spmr 8 8 2 or 3 pclkb 0008 a020h sci1 serial mode register smr 8 8 2 or 3 pclkb 0008 a021h sci1 bit rate register brr 8 8 2 or 3 pclkb 0008 a022h sci1 serial control register scr 8 8 2 or 3 pclkb 0008 a023h sci1 transmit data register tdr 8 8 2 or 3 pclkb 0008 a024h sci1 serial status register ssr 8 8 2 or 3 pclkb 0008 a025h sci1 receive data register rdr 8 8 2 or 3 pclkb 0008 a026h sci1 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a027h sci1 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a028h sci1 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (12/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 42 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a02ch sci1 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a02dh sci1 spi mode register spmr 8 8 2 or 3 pclkb 0008 a040h sci2 serial mode register smr 8 8 2 or 3 pclkb 0008 a041h sci2 bit rate register brr 8 8 2 or 3 pclkb 0008 a042h sci2 serial control register scr 8 8 2 or 3 pclkb 0008 a043h sci2 transmit data register tdr 8 8 2 or 3 pclkb 0008 a044h sci2 serial status register ssr 8 8 2 or 3 pclkb 0008 a045h sci2 receive data register rdr 8 8 2 or 3 pclkb 0008 a046h sci2 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a047h sci2 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a048h sci2 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a049h sci2 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a04ah sci2 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a04bh sci2 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a04ch sci2 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a04dh sci2 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0a0h sci5 serial mode register smr 8 8 2 or 3 pclkb 0008 a0a1h sci5 bit rate register brr 8 8 2 or 3 pclkb 0008 a0a2h sci5 serial control register scr 8 8 2 or 3 pclkb 0008 a0a3h sci5 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0a4h sci5 serial status register ssr 8 8 2 or 3 pclkb 0008 a0a5h sci5 receive data register rdr 8 8 2 or 3 pclkb 0008 a0a6h sci5 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0a7h sci5 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0a8h sci5 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0ach sci5 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0adh sci5 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0c0h sci6 serial mode register smr 8 8 2 or 3 pclkb 0008 a0c1h sci6 bit rate register brr 8 8 2 or 3 pclkb 0008 a0c2h sci6 serial control register scr 8 8 2 or 3 pclkb 0008 a0c3h sci6 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0c4h sci6 serial status register ssr 8 8 2 or 3 pclkb 0008 a0c5h sci6 receive data register rdr 8 8 2 or 3 pclkb 0008 a0c6h sci6 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0c7h sci6 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0c8h sci6 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0cch sci6 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0cdh sci6 spi mode register spmr 8 8 2 or 3 pclkb 0008 a100h sci8 serial mode register smr 8 8 2 or 3 pclkb 0008 a101h sci8 bit rate register brr 8 8 2 or 3 pclkb 0008 a102h sci8 serial control register scr 8 8 2 or 3 pclkb 0008 a103h sci8 transmit data register tdr 8 8 2 or 3 pclkb 0008 a104h sci8 serial status register ssr 8 8 2 or 3 pclkb 0008 a105h sci8 receive data register rdr 8 8 2 or 3 pclkb 0008 a106h sci8 smart card mode register scmr 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (13/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 43 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 a107h sci8 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a108h sci8 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a109h sci8 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a10ah sci8 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a10bh sci8 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a10ch sci8 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a10dh sci8 spi mode register spmr 8 8 2 or 3 pclkb 0008 a120h sci9 serial mode register smr 8 8 2 or 3 pclkb 0008 a121h sci9 bit rate register brr 8 8 2 or 3 pclkb 0008 a122h sci9 serial control register scr 8 8 2 or 3 pclkb 0008 a123h sci9 transmit data register tdr 8 8 2 or 3 pclkb 0008 a124h sci9 serial status register ssr 8 8 2 or 3 pclkb 0008 a125h sci9 receive data register rdr 8 8 2 or 3 pclkb 0008 a126h sci9 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a127h sci9 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a128h sci9 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a129h sci9 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a12ah sci9 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a12bh sci9 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a12ch sci9 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a12dh sci9 spi mode register spmr 8 8 2 or 3 pclkb 0008 a500h ssi0 control register ssicr 32 32 2 or 3 pclkb 0008 a504h ssi0 status register ssisr 32 32 2 or 3 pclkb 0008 a510h ssi0 fifo control register ssifcr 32 32 2 or 3 pclkb 0008 a514h ssi0 fifo status register ssifsr 32 32 2 or 3 pclkb 0008 a518h ssi0 transmit fifo data register ssiftdr 32 32 2 or 3 pclkb 0008 a51ch ssi0 receive fifo data register ssifrdr 32 32 2 or 3 pclkb 0008 a520h ssi0 tdm mode register ssitdmr 32 32 2 or 3 pclkb 0008 b000h cac cac control register 0 cacr0 8 8 2 or 3 pclkb 0008 b001h cac cac control register 1 cacr1 8 8 2 or 3 pclkb 0008 b002h cac cac control register 2 cacr2 8 8 2 or 3 pclkb 0008 b003h cac cac interrupt request enable register caicr 8 8 2 or 3 pclkb 0008 b004h cac cac status register castr 8 8 2 or 3 pclkb 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2 or 3 pclkb 0008 b008h cac cac lower-limit value setting register callvr 16 16 2 or 3 pclkb 0008 b00ah cac cac counter buffer register cacntbr 16 16 2 or 3 pclkb 0008 b080h doc doc control register docr 8 8 2 or 3 pclkb 0008 b082h doc doc data input register dodir 16 16 2 or 3 pclkb 0008 b084h doc doc data setting register dodsr 16 16 2 or 3 pclkb 0008 b100h elc event link control register elcr 8 8 2 or 3 pclkb 0008 b102h elc event link setting register 1 elsr1 8 8 2 or 3 pclkb 0008 b103h elc event link setting register 2 elsr2 8 8 2 or 3 pclkb 0008 b104h elc event link setting register 3 elsr3 8 8 2 or 3 pclkb 0008 b105h elc event link setting register 4 elsr4 8 8 2 or 3 pclkb 0008 b108h elc event link setting register 7 elsr7 8 8 2 or 3 pclkb 0008 b10bh elc event link setting register 10 elsr10 8 8 2 or 3 pclkb 0008 b10dh elc event link setting register 12 elsr12 8 8 2 or 3 pclkb 0008 b10fh elc event link setting register 14 elsr14 8 8 2 or 3 pclkb 0008 b110h elc event link setting register 15 elsr15 8 8 2 or 3 pclkb 0008 b112h elc event link setting register 17 elsr17 8 8 2 or 3 pclkb 0008 b113h elc event link setting register 18 elsr18 8 8 2 or 3 pclkb 0008 b115h elc event link setting register 20 elsr20 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (14/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 44 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 b117h elc event link setting register 22 elsr22 8 8 2 or 3 pclkb 0008 b119h elc event link setting register 24 elsr24 8 8 2 or 3 pclkb 0008 b11ah elc event link setting register 25 elsr25 8 8 2 or 3 pclkb 0008 b11fh elc event link option setting register a elopa 8 8 2 or 3 pclkb 0008 b120h elc event link option setting register b elopb 8 8 2 or 3 pclkb 0008 b121h elc event link option setting register c elopc 8 8 2 or 3 pclkb 0008 b122h elc event link option setting register d elopd 8 8 2 or 3 pclkb 0008 b123h elc port group setting register 1 pgr1 8 8 2 or 3 pclkb 0008 b125h elc port group control register 1 pgc1 8 8 2 or 3 pclkb 0008 b127h elc port buffer register 1 pdbf1 8 8 2 or 3 pclkb 0008 b129h elc event link port setting register 0 pel0 8 8 2 or 3 pclkb 0008 b12ah elc event link port setting register 1 pel1 8 8 2 or 3 pclkb 0008 b12dh elc event link software event generation register elsegr 8 8 2 or 3 pclkb 0008 b300h sci12 serial mode register smr 8 8 2 or 3 pclkb 0008 b301h sci12 bit rate register brr 8 8 2 or 3 pclkb 0008 b302h sci12 serial control register scr 8 8 2 or 3 pclkb 0008 b303h sci12 transmit data register tdr 8 8 2 or 3 pclkb 0008 b304h sci12 serial status register ssr 8 8 2 or 3 pclkb 0008 b305h sci12 receive data register rdr 8 8 2 or 3 pclkb 0008 b306h sci12 smart card mode register scmr 8 8 2 or 3 pclkb 0008 b307h sci12 serial extended mode register semr 8 8 2 or 3 pclkb 0008 b308h sci12 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 b30ch sci12 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 b30dh sci12 spi mode register spmr 8 8 2 or 3 pclkb 0008 b320h sci12 extended serial mode enable register esmer 8 8 2 or 3 pclkb 0008 b321h sci12 control register 0 cr0 8 8 2 or 3 pclkb 0008 b322h sci12 control register 1 cr1 8 8 2 or 3 pclkb 0008 b323h sci12 control register 2 cr2 8 8 2 or 3 pclkb 0008 b324h sci12 control register 3 cr3 8 8 2 or 3 pclkb 0008 b325h sci12 port control register pcr 8 8 2 or 3 pclkb 0008 b326h sci12 interrupt control register icr 8 8 2 or 3 pclkb 0008 b327h sci12 status register str 8 8 2 or 3 pclkb 0008 b328h sci12 status clear register stcr 8 8 2 or 3 pclkb 0008 b329h sci12 control field 0 data register cf0dr 8 8 2 or 3 pclkb 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2 or 3 pclkb 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2 or 3 pclkb 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2 or 3 pclkb 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2 or 3 pclkb 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2 or 3 pclkb 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2 or 3 pclkb 0008 b330h sci12 timer control register tcr 8 8 2 or 3 pclkb 0008 b331h sci12 timer mode register tmr 8 8 2 or 3 pclkb 0008 b332h sci12 timer prescaler register tpre 8 8 2 or 3 pclkb 0008 b333h sci12 timer count register tcnt 8 8 2 or 3 pclkb 0008 c000h port0 port direction register pdr 8 8 2 or 3 pclkb 0008 c001h port1 port direction register pdr 8 8 2 or 3 pclkb 0008 c002h port2 port direction register pdr 8 8 2 or 3 pclkb 0008 c003h port3 port direction register pdr 8 8 2 or 3 pclkb 0008 c004h port4 port direction register pdr 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (15/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 45 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 c005h port5 port direction register pdr 8 8 2 or 3 pclkb 0008 c009h port9 port direction register pdr 8 8 2 or 3 pclkb 0008 c00ah porta port direction register pdr 8 8 2 or 3 pclkb 0008 c00bh portb port direction register pdr 8 8 2 or 3 pclkb 0008 c00ch portc port direction register pdr 8 8 2 or 3 pclkb 0008 c00dh portd port direction register pdr 8 8 2 or 3 pclkb 0008 c00eh porte port direction register pdr 8 8 2 or 3 pclkb 0008 c00fh portf port direction register pdr 8 8 2 or 3 pclkb 0008 c012h portj port direction register pdr 8 8 2 or 3 pclkb 0008 c020h port0 port output data register podr 8 8 2 or 3 pclkb 0008 c021h port1 port output data register podr 8 8 2 or 3 pclkb 0008 c022h port2 port output data register podr 8 8 2 or 3 pclkb 0008 c023h port3 port output data register podr 8 8 2 or 3 pclkb 0008 c024h port4 port output data register podr 8 8 2 or 3 pclkb 0008 c025h port5 port output data register podr 8 8 2 or 3 pclkb 0008 c029h port9 port output data register podr 8 8 2 or 3 pclkb 0008 c02ah porta port output data register podr 8 8 2 or 3 pclkb 0008 c02bh portb port output data register podr 8 8 2 or 3 pclkb 0008 c02ch portc port output data register podr 8 8 2 or 3 pclkb 0008 c02dh portd port output data register podr 8 8 2 or 3 pclkb 0008 c02eh porte port output data register podr 8 8 2 or 3 pclkb 0008 c02fh portf port output data register podr 8 8 2 or 3 pclkb 0008 c032h portj port output data register podr 8 8 2 or 3 pclkb 0008 c040h port0 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c041h port1 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c042h port2 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c043h port3 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c044h port4 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c045h port5 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c049h port9 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04ah porta port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04bh portb port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04ch portc port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04dh portd port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing table 4.1 list of i/o registers (address order) (16/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 46 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 c04eh porte port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04fh portf port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c051h porth port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c052h portj port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c060h port0 port mode register pmr 8 8 2 or 3 pclkb 0008 c061h port1 port mode register pmr 8 8 2 or 3 pclkb 0008 c062h port2 port mode register pmr 8 8 2 or 3 pclkb 0008 c063h port3 port mode register pmr 8 8 2 or 3 pclkb 0008 c064h port4 port mode register pmr 8 8 2 or 3 pclkb 0008 c065h port5 port mode register pmr 8 8 2 or 3 pclkb 0008 c069h port9 port mode register pmr 8 8 2 or 3 pclkb 0008 c06ah porta port mode register pmr 8 8 2 or 3 pclkb 0008 c06bh portb port mode register pmr 8 8 2 or 3 pclkb 0008 c06ch portc port mode register pmr 8 8 2 or 3 pclkb 0008 c06dh portd port mode register pmr 8 8 2 or 3 pclkb 0008 c06eh porte port mode register pmr 8 8 2 or 3 pclkb 0008 c06fh portf port mode register pmr 8 8 2 or 3 pclkb 0008 c071h porth port mode register pmr 8 8 2 or 3 pclkb 0008 c072h portj port mode register pmr 8 8 2 or 3 pclkb 0008 c080h port0 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c081h port0 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c084h port2 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c08ah port5 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c08bh port5 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c094h porta open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c095h porta open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c096h portb open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c097h portb open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c098h portc open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c099h portc open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c09dh porte open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c0a4h portj open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c0c0h port0 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c1h port1 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c2h port2 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c3h port3 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c5h port5 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cah porta pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cbh portb pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cch portc pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cdh portd pull-up control register pcr 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (17/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 47 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 c0ceh porte pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cfh portf pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0d2h portj pull-up control register pcr 8 8 2 or 3 pclkb 0008 c11fh mpc write-protect register pwpr 8 8 2 or 3 pclkb 0008 c121h port port switching register a psra 8 8 2 or 3 pclkb 0008 c142h mpc p02 pin function control register p02pfs 8 8 2 or 3 pclkb 0008 c144h mpc p04 pin function control register p04pfs 8 8 2 or 3 pclkb 0008 c147h mpc p07 pin function control register p07pfs 8 8 2 or 3 pclkb 0008 c148h mpc p10 pin function control register p10pfs 8 8 2 or 3 pclkb 0008 c149h mpc p11 pin function control register p11pfs 8 8 2 or 3 pclkb 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2 or 3 pclkb 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2 or 3 pclkb 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2 or 3 pclkb 0008 c14dh mpc p15 pin function control register p15pfs 8 8 2 or 3 pclkb 0008 c14eh mpc p16 pin function control register p16pfs 8 8 2 or 3 pclkb 0008 c14fh mpc p17 pin function control register p17pfs 8 8 2 or 3 pclkb 0008 c150h mpc p20 pin function control register p20pfs 8 8 2 or 3 pclkb 0008 c151h mpc p21 pin function control register p21pfs 8 8 2 or 3 pclkb 0008 c152h mpc p22 pin function control register p22pfs 8 8 2 or 3 pclkb 0008 c153h mpc p23 pin function control register p23pfs 8 8 2 or 3 pclkb 0008 c154h mpc p24 pin function control register p24pfs 8 8 2 or 3 pclkb 0008 c155h mpc p25 pin function control register p25pfs 8 8 2 or 3 pclkb 0008 c156h mpc p26 pin function control register p26pfs 8 8 2 or 3 pclkb 0008 c157h mpc p27 pin function control register p27pfs 8 8 2 or 3 pclkb 0008 c158h mpc p30 pin function control register p30pfs 8 8 2 or 3 pclkb 0008 c159h mpc p31 pin function control register p31pfs 8 8 2 or 3 pclkb 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2 or 3 pclkb 0008 c160h mpc p40 pin function control register p40pfs 8 8 2 or 3 pclkb 0008 c161h mpc p41 pin function control register p41pfs 8 8 2 or 3 pclkb 0008 c162h mpc p42 pin function control register p42pfs 8 8 2 or 3 pclkb 0008 c163h mpc p43 pin function control register p43pfs 8 8 2 or 3 pclkb 0008 c164h mpc p44 pin function control register p44pfs 8 8 2 or 3 pclkb 0008 c166h mpc p46 pin function control register p46pfs 8 8 2 or 3 pclkb 0008 c168h mpc p50 pin function control register p50pfs 8 8 2 or 3 pclkb 0008 c169h mpc p51 pin function control register p51pfs 8 8 2 or 3 pclkb 0008 c16ah mpc p52 pin function control register p52pfs 8 8 2 or 3 pclkb 0008 c16bh mpc p53 pin function control register p53pfs 8 8 2 or 3 pclkb 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2 or 3 pclkb 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2 or 3 pclkb 0008 c16eh mpc p56 pin function control register p56pfs 8 8 2 or 3 pclkb 0008 c188h mpc p90 pin function control register p90pfs 8 8 2 or 3 pclkb 0008 c189h mpc p91 pin function control register p91pfs 8 8 2 or 3 pclkb 0008 c18ah mpc p92 pin function control register p92pfs 8 8 2 or 3 pclkb 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2 or 3 pclkb 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2 or 3 pclkb 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2 or 3 pclkb 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2 or 3 pclkb 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2 or 3 pclkb 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2 or 3 pclkb 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2 or 3 pclkb 0008 c197h mpc pa7 pin function control register pa7pfs 8 8 2 or 3 pclkb 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (18/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 48 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2 or 3 pclkb 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2 or 3 pclkb 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2 or 3 pclkb 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2 or 3 pclkb 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2 or 3 pclkb 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2 or 3 pclkb 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2 or 3 pclkb 0008 c1a0h mpc pc0 pin function control register pc0pfs 8 8 2 or 3 pclkb 0008 c1a1h mpc pc1 pin function control register pc1pfs 8 8 2 or 3 pclkb 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2 or 3 pclkb 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2 or 3 pclkb 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2 or 3 pclkb 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2 or 3 pclkb 0008 c1a6h mpc pc6 pin function control register pc6pfs 8 8 2 or 3 pclkb 0008 c1a7h mpc pc7 pin function control register pc7pfs 8 8 2 or 3 pclkb 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2 or 3 pclkb 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2 or 3 pclkb 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2 or 3 pclkb 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2 or 3 pclkb 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2 or 3 pclkb 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2 or 3 pclkb 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2 or 3 pclkb 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2 or 3 pclkb 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2 or 3 pclkb 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2 or 3 pclkb 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2 or 3 pclkb 0008 c1b6h mpc pe6 pin function control register pe6pfs 8 8 2 or 3 pclkb 0008 c1b7h mpc pe7 pin function control register pe7pfs 8 8 2 or 3 pclkb 0008 c1beh mpc pf6 pin function control register pf6pfs 8 8 2 or 3 pclkb 0008 c1bfh mpc pf7 pin function control register pf7pfs 8 8 2 or 3 pclkb 0008 c1d0h mpc pj0 pin function control register pj0pfs 8 8 2 or 3 pclkb 0008 c1d2h mpc pj2 pin function control register pj2pfs 8 8 2 or 3 pclkb 0008 c1d3h mpc pj3 pin function control register pj3pfs 8 8 2 or 3 pclkb 0008 c1d6h mpc pj6 pin function control register pj6pfs 8 8 2 or 3 pclkb 0008 c1d7h mpc pj7 pin function control register pj7pfs 8 8 2 or 3 pclkb 0008 c290h system reset status register 0 rstsr0 8 8 4 or 5 pclkb 0008 c291h system reset status register 1 rstsr1 8 8 4 or 5 pclkb 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4 or 5 pclkb 0008 c297h system voltage monitoring circuit control register lvcmpcr 8 8 4 or 5 pclkb 0008 c298h system voltage detection level select register lvdlvlr 8 8 4 or 5 pclkb 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4 or 5 pclkb 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4 or 5 pclkb 0008 c400h rtc 64-hz counter r64cnt 8 8 2 or 3 pclkb 0008 c402h rtc second counter rseccnt 8 8 2 or 3 pclkb 0008 c402h rtc binary counter 0 bcnt0 8 8 2 or 3 pclkb 0008 c404h rtc minute counter rmincnt 8 8 2 or 3 pclkb 0008 c404h rtc binary counter 1 bcnt1 8 8 2 or 3 pclkb 0008 c406h rtc hour counter rhrcnt 8 8 2 or 3 pclkb 0008 c406h rtc binary counter 2 bcnt2 8 8 2 or 3 pclkb 0008 c408h rtc day-of-week counter rwkcnt 8 8 2 or 3 pclkb 0008 c408h rtc binary counter 3 bcnt3 8 8 2 or 3 pclkb 0008 c40ah rtc date counter rdaycnt 8 8 2 or 3 pclkb table 4.1 list of i/o registers (address order) (19/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 49 of 121 dec 01, 2014 rx113 group 4. i/o registers 0008 c40ch rtc month counter rmoncnt 8 8 2 or 3 pclkb 0008 c40eh rtc year counter ryrcnt 16 16 2 or 3 pclkb 0008 c410h rtc second alarm register rsecar 8 8 2 or 3 pclkb 0008 c410h rtc binary counter 0 alarm register bcnt0ar 8 8 2 or 3 pclkb 0008 c412h rtc minute alarm register rminar 8 8 2 or 3 pclkb 0008 c412h rtc binary counter 1 alarm register bcnt1ar 8 8 2 or 3 pclkb 0008 c414h rtc hour alarm register rhrar 8 8 2 or 3 pclkb 0008 c414h rtc binary counter 2 alarm register bcnt2ar 8 8 2 or 3 pclkb 0008 c416h rtc day-of-week alarm register rwkar 8 8 2 or 3 pclkb 0008 c416h rtc binary counter 3 alarm register bcnt3ar 8 8 2 or 3 pclkb 0008 c418h rtc date alarm register rdayar 8 8 2 or 3 pclkb 0008 c418h rtc binary counter 0 alarm enable register bcnt0aer 8 8 2 or 3 pclkb 0008 c41ah rtc month alarm register rmonar 8 8 2 or 3 pclkb 0008 c41ah rtc binary counter 1 alarm enable register bcnt1aer 8 8 2 or 3 pclkb 0008 c41ch rtc year alarm register ryrar 16 16 2 or 3 pclkb 0008 c41ch rtc binary counter 2 alarm enable register bcnt2aer 16 16 2 or 3 pclkb 0008 c41eh rtc year alarm enable register ryraren 8 8 2 or 3 pclkb 0008 c41eh rtc binary counter 3 alarm enable register bcnt3aer 8 8 2 or 3 pclkb 0008 c422h rtc rtc control register 1 rcr1 8 8 2 or 3 pclkb 0008 c424h rtc rtc control register 2 rcr2 8 8 2 or 3 pclkb 0008 c426h rtc rtc control register 3 rcr3 8 8 2 or 3 pclkb 0008 c42eh rtc time error adjustment register radj 8 8 2 or 3 pclkb 0008 c580h cmpb comparator b control register 1 cpbcnt1 8 8 2 or 3 pclkb 0008 c581h cmpb comparator b control register 2 cpbcnt2 8 8 2 or 3 pclkb 0008 c582h cmpb comparator b flag register cpbflg 8 8 2 or 3 pclkb 0008 c583h cmpb comparator b interrupt control register cpbint 8 8 2 or 3 pclkb 0008 c584h cmpb comparator b filter select register cpbf 8 8 2 or 3 pclkb 0008 c585h cmpb comparator b mode select register cpbmd 8 8 2 or 3 pclkb 0008 c586h cmpb comparator b reference input voltage select register cpbref 8 8 2 or 3 pclkb 0008 c587h cmpb comparator b output control register cpbocr 8 8 2 or 3 pclkb 000a 0000h usb0 system configuration control register syscfg 16 16 3 or 4 pclkb 000a 0004h usb0 system configuration status register 0 syssts0 16 16 9 pclk or more 000a 0008h usb0 device state control register 0 dvstctr0 16 16 9 pclk or more 000a 0014h usb0 cfifo port register cfifo 16 16 3 or 4 pclkb 000a 0018h usb0 d0fifo port register d0fifo 16 16 3 or 4 pclkb 000a 001ch usb0 d1fifo port register d1fifo 16 16 3 or 4 pclkb 000a 0020h usb0 cfifo port select register cfifosel 16 16 3 or 4 pclkb 000a 0028h usb0 d0fifo port select register d0fifosel 16 16 3 or 4 pclkb 000a 002ch usb0 d1fifo port select register d1fifosel 16 16 3 or 4 pclkb 000a 0022h usb0 cfifo port control register cfifoctr 16 16 3 or 4 pclkb 000a 002ah usb0 d0fifo port control register d0fifoctr 16 16 3 or 4 pclkb 000a 002eh usb0 d1fifo port control register d1fifoctr 16 16 3 or 4 pclkb 000a 0030h usb0 interrupt enable register 0 intenb0 16 16 9 pclkb or more 000a 0032h usb0 interrupt enable register 1 intenb1 16 16 9 pclkb or more 000a 0036h usb0 brdy interrupt enable register brdyenb 16 16 9 pclkb or more 000a 0038h usb0 nrdy interrupt enable register nrdyenb 16 16 9 pclkb or more 000a 003ah usb0 bemp interrupt enable register bempenb 16 16 9 pclkb or more 000a 003ch usb0 sof output configuration register sofcfg 16 16 9 pclkb or more 000a 0040h usb0 interrupt status register 0 intsts0 16 16 9 pclkb or more 000a 0042h usb0 interrupt status register 1 intsts1 16 16 9 pclkb or more 000a 0046h usb0 brdy interrupt status register brdysts 16 16 9 pclkb or more 000a 0048h usb0 nrdy interrupt status register nrdysts 16 16 9 pclkb or more table 4.1 list of i/o registers (address order) (20/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 50 of 121 dec 01, 2014 rx113 group 4. i/o registers 000a 004ah usb0 bemp interrupt status register bempsts 16 16 9 pclkb or more 000a 004ch usb0 frame number register frmnum 16 16 9 pclkb or more 000a 0054h usb0 usb request type register usbreq 16 16 9 pclkb or more 000a 0056h usb0 usb request value register usbval 16 16 9 pclkb or more 000a 0058h usb0 usb request index register usbindx 16 16 9 pclkb or more 000a 005ah usb0 usb request length register usbleng 16 16 9 pclkb or more 000a 005ch usb0 dcp configuration register dcpcfg 16 16 9 pclkb or more 000a 005eh usb0 dcp maximum packet size register dcpmaxp 16 16 9 pclkb or more 000a 0060h usb0 dcp control register dcpctr 16 16 9 pclkb or more 000a 0064h usb0 pipe window select register pipesel 16 16 9 pclkb or more 000a 0068h usb0 pipe configuration register pipecfg 16 16 9 pclkb or more 000a 006ch usb0 pipe maximum packet size register pipemaxp 16 16 9 pclkb or more 000a 006eh usb0 pipe cycle control register pipeperi 16 16 9 pclkb or more 000a 0070h usb0 pipe1 control register pipe1ctr 16 16 9 pclkb or more 000a 0072h usb0 pipe2 control register pipe2ctr 16 16 9 pclkb or more 000a 0074h usb0 pipe3 control register pipe3ctr 16 16 9 pclkb or more 000a 0076h usb0 pipe4 control register pipe4ctr 16 16 9 pclkb or more 000a 0078h usb0 pipe5 control register pipe5ctr 16 16 9 pclkb or more 000a 007ah usb0 pipe6 control register pipe6ctr 16 16 9 pclkb or more 000a 007ch usb0 pipe7 control register pipe7ctr 16 16 9 pclkb or more 000a 007eh usb0 pipe8 control register pipe8ctr 16 16 9 pclkb or more 000a 0080h usb0 pipe9 control register pipe9ctr 16 16 9 pclkb or more 000a 0090h usb0 pipe1 transaction counter enable register pipe1tre 16 16 9 pclkb or more 000a 0092h usb0 pipe1 transaction counter register pipe1trn 16 16 9 pclkb or more 000a 0094h usb0 pipe2 transaction counter enable register pipe2tre 16 16 9 pclkb or more 000a 0096h usb0 pipe2 transaction counter register pipe2trn 16 16 9 pclkb or more 000a 0098h usb0 pipe3 transaction counter enable register pipe3tre 16 16 9 pclkb or more 000a 009ah usb0 pipe3 transaction counter register pipe3trn 16 16 9 pclkb or more 000a 009ch usb0 pipe4 transaction counter enable register pipe4tre 16 16 9 pclkb or more 000a 009eh usb0 pipe4 transaction counter register pipe4trn 16 16 9 pclkb or more 000a 00a0h usb0 pipe5 transaction counter enable register pipe5tre 16 16 9 pclkb or more 000a 00a2h usb0 pipe5 transaction counter register pipe5trn 16 16 9 pclkb or more 000a 00b0h usb0 bc control register 0 usbbcctrl0 16 16 9 pclkb or more 000a 00cch usb0 usb module control register usbmc 16 16 9 pclkb or more 000a 00d0h usb0 device address 0 configuration register devadd0 16 16 9 pclkb or more 000a 00d2h usb0 device address 1 configuration register devadd1 16 16 9 pclkb or more 000a 00d4h usb0 device address 2 configuration register devadd2 16 16 9 pclkb or more 000a 00d6h usb0 device address 3 configuration register devadd3 16 16 9 pclkb or more 000a 00d8h usb0 device address 4 configuration register devadd4 16 16 9 pclkb or more 000a 00dah usb0 device address 5 configuration register devadd5 16 16 9 pclkb or more 000a 0800h lcdc lcd mode register 0 lcdm0 8 8 1 or 2 pclkb 000a 0801h lcdc lcd mode register 1 lcdm1 8 8 1 or 2 pclkb 000a 0802h lcdc lcd clock control register 0 lcdc0 8 8 1 or 2 pclkb 000a 0803h lcdc lcd boost level control register vlcd 8 8 1 or 2 pclkb 000a 0840h lcdc lcd display data register 00 seg00 8 8 1 or 2 pclkb 000a 0841h lcdc lcd display data register 01 seg01 8 8 1 or 2 pclkb 000a 0842h lcdc lcd display data register 02 seg02 8 8 1 or 2 pclkb 000a 0843h lcdc lcd display data register 03 seg03 8 8 1 or 2 pclkb 000a 0844h lcdc lcd display data register 04 seg04 8 8 1 or 2 pclkb 000a 0845h lcdc lcd display data register 05 seg05 8 8 1 or 2 pclkb 000a 0846h lcdc lcd display data register 06 seg06 8 8 1 or 2 pclkb 000a 0847h lcdc lcd display data register 07 seg07 8 8 1 or 2 pclkb table 4.1 list of i/o registers (address order) (21/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 51 of 121 dec 01, 2014 rx113 group 4. i/o registers 000a 0848h lcdc lcd display data register 08 seg08 8 8 1 or 2 pclkb 000a 0849h lcdc lcd display data register 09 seg09 8 8 1 or 2 pclkb 000a 084ah lcdc lcd display data register 10 seg10 8 8 1 or 2 pclkb 000a 084bh lcdc lcd display data register 11 seg11 8 8 1 or 2 pclkb 000a 084ch lcdc lcd display data register 12 seg12 8 8 1 or 2 pclkb 000a 084dh lcdc lcd display data register 13 seg13 8 8 1 or 2 pclkb 000a 084eh lcdc lcd display data register 14 seg14 8 8 1 or 2 pclkb 000a 084fh lcdc lcd display data register 15 seg15 8 8 1 or 2 pclkb 000a 0850h lcdc lcd display data register 16 seg16 8 8 1 or 2 pclkb 000a 0851h lcdc lcd display data register 17 seg17 8 8 1 or 2 pclkb 000a 0852h lcdc lcd display data register 18 seg18 8 8 1 or 2 pclkb 000a 0853h lcdc lcd display data register 19 seg19 8 8 1 or 2 pclkb 000a 0854h lcdc lcd display data register 20 seg20 8 8 1 or 2 pclkb 000a 0855h lcdc lcd display data register 21 seg21 8 8 1 or 2 pclkb 000a 0856h lcdc lcd display data register 22 seg22 8 8 1 or 2 pclkb 000a 0857h lcdc lcd display data register 23 seg23 8 8 1 or 2 pclkb 000a 0858h lcdc lcd display data register 24 seg24 8 8 1 or 2 pclkb 000a 0859h lcdc lcd display data register 25 seg25 8 8 1 or 2 pclkb 000a 085ah lcdc lcd display data register 26 seg26 8 8 1 or 2 pclkb 000a 085bh lcdc lcd display data register 27 seg27 8 8 1 or 2 pclkb 000a 085ch lcdc lcd display data register 28 seg28 8 8 1 or 2 pclkb 000a 085dh lcdc lcd display data register 29 seg29 8 8 1 or 2 pclkb 000a 085eh lcdc lcd display data register 30 seg30 8 8 1 or 2 pclkb 000a 085fh lcdc lcd display data register 31 seg31 8 8 1 or 2 pclkb 000a 0860h lcdc lcd display data register 32 seg32 8 8 1 or 2 pclkb 000a 0861h lcdc lcd display data register 33 seg33 8 8 1 or 2 pclkb 000a 0862h lcdc lcd display data register 34 seg34 8 8 1 or 2 pclkb 000a 0863h lcdc lcd display data register 35 seg35 8 8 1 or 2 pclkb 000a 0864h lcdc lcd display data register 36 seg36 8 8 1 or 2 pclkb 000a 0865h lcdc lcd display data register 37 seg37 8 8 1 or 2 pclkb 000a 0866h lcdc lcd display data register 38 seg38 8 8 1 or 2 pclkb 000a 0867h lcdc lcd display data register 39 seg39 8 8 1 or 2 pclkb 000a 0900h ctsu ctsu control register 0 ctsucr0 8 8 1 or 2 pclkb 000a 0901h ctsu ctsu control register 1 ctsucr1 8 8 1 or 2 pclkb 000a 0902h ctsu ctsu synchronous noise reduction setting register ctsusdprs 8 8 1 or 2 pclkb 000a 0903h ctsu ctsu sensor stabilization wait time register ctsusst 8 8 1 or 2 pclkb 000a 0904h ctsu ctsu measurement channel register 0 ctsumch0 8 8 1 or 2 pclkb 000a 0905h ctsu ctsu measurement channel register 1 ctsumch1 8 8 1 or 2 pclkb 000a 0906h ctsu ctsu channel enable control register 0 ctsuchac0 8 8 1 or 2 pclkb 000a 0907h ctsu ctsu channel enable control register 1 ctsuchac1 8 8 1 or 2 pclkb 000a 090bh ctsu ctsu channel transmit/receive control register 0 ctsuchtrc0 8 8 1 or 2 pclkb 000a 090ch ctsu ctsu channel transmit/receive control register 1 ctsuchtrc1 8 8 1 or 2 pclkb 000a 0910h ctsu ctsu high-pass noise reduction control register ctsudclkc 8 8 1 or 2 pclkb 000a 0911h ctsu ctsu status register ctsust 8 8 1 or 2 pclkb 000a 0912h ctsu ctsu high-pass noise spectrum diffusion control register ctsussc 16 16 1 or 2 pclkb 000a 0914h ctsu ctsu sensor offset register 0 ctsuso0 16 16 1 or 2 pclkb 000a 0916h ctsu ctsu sensor offset register 1 ctsuso1 16 16 1 or 2 pclkb 000a 0918h ctsu ctsu sensor counter ctsusc 16 16 1 or 2 pclkb 000a 091ah ctsu ctsu reference counter ctsurc 16 16 1 or 2 pclkb 000a 091ch ctsu ctsu error status register ctsuerrs 16 16 1 or 2 pclkb 007f c090h flash e2 dataflash control register dflctl 8 8 2 or 3 fclk 007f c0ach temps temperature sensor calibration data register tscdrl 8 8 1 or 2 pclkb table 4.1 list of i/o registers (address order) (22/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 52 of 121 dec 01, 2014 rx113 group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. when accessing a register in 16-bit units, access the address of the t mr0 or tmr2 register. note 2. odd addresses cannot be accessed in 16-bit units. when accessing a register in 16-bit units, access the address of the tmocntl register. 007f c0adh temps temperature sensor calibration data register tscdrh 8 8 1 or 2 pclkb 007f c0b0h flash flash start-up setting monitor register fscmr 16 16 2 or 3 fclk 007f c0b2h flash flash access window start address monitor fawsmr 16 16 2 or 3 fclk 007f c0b4h flash flash access window end address monitor register fawemr 16 16 2 or 3 fclk 007f c0b6h flash flash initial setting register fisr 8 8 2 or 3 fclk 007f c0b7h flash flash extra area control register fexcr 8 8 2 or 3 fclk 007f c0b8h flash flash error address monitor register l feaml 16 16 2 or 3 fclk 007f c0bah flash flash error address monitor register h feamh 8 8 2 or 3 fclk 007f c0c0h flash protection unlock register fpr 8 8 2 or 3 fclk 007f c0c1h flash protection unlock status register fpsr 8 8 2 or 3 fclk 007f c0c2h flash flash read buffer register l frbl 16 16 2 or 3 fclk 007f c0c4h flash flash read buffer register h frbh 16 16 2 or 3 fclk 007f ff80h flash flash p/e mode control register fpmcr 8 8 2 or 3 fclk 007f ff81h flash flash area select register fasr 8 8 2 or 3 fclk 007f ff82h flash flash processing start address register l fsarl 16 16 2 or 3 fclk 007f ff84h flash flash processing start address register h fsarh 8 8 2 or 3 fclk 007f ff85h flash flash control register fcr 8 8 2 or 3 fclk 007f ff86h flash flash processing end address register l fearl 16 16 2 or 3 fclk 007f ff88h flash flash processing end address register h fearh 8 8 2 or 3 fclk 007f ff89h flash flash reset register fresetr 8 8 2 or 3 fclk 007f ff8ah flash flash status register 0 fstatr0 8 8 2 or 3 fclk 007f ff8bh flash flash status register 1 fstatr1 8 8 2 or 3 fclk 007f ff8ch flash flash write buffer register l fwbl 16 16 2 or 3 fclk 007f ff8eh flash flash write buffer register h fwbh 16 16 2 or 3 fclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 or 3 fclk table 4.1 list of i/o registers (address order) (23/23) address module symbol register name register symbol number of bits access size number of access states
r01ds0216ej0102 rev.1.02 page 53 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the mcu may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, between t he vcc_usb and vss_usb pins, between the vrefh0 and vrefl0 pins, and between the vrefh and vref l pins. place capacitors of about 0.1 f as close as possible to every power supply pin and use the shortest and heaviest possible traces. also, connect capacitors as stabilization capacitance. connect the vcl pin to a vss pin via a 4.7 f capacitor. the capacitor must be placed close to the pin. note 1. ports 16, 17, a6, and b0 are 5 v tolerant. do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from in put of such a signal or i/o pull-up may cause malfunction and the abnorm al current that passes in the device at this time may cause degradation of internal elements. note 2. the upper limit of operating temperature is 85c or 105c, depending on the product. for details, refer to table 1.3, li st of products. note 1. avcc0 and vcc can be set individually within the operatin g range, but there is the following relationship between the vo ltage applied to the pj0 and pj2 pins, vcc, and avcc0. when 12-bit d/a converter used: voltage applied to port j0 and j2 pins (d/a output voltage) vcc when general ports selected: vcc avcc0 note 2. sequence of powering on avcc0 and vcc when powering on avcc0 and vcc, power them on at the same time or vcc first. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl0 = vrefl = vss_usb = 0 v item symbol value unit power supply voltage vcc, vcc_usb ?0.3 to +4.6 v input voltage (except for ports for 5 v tolerant* 1 )v in ?0.3 to vcc + 0.3 v input voltage (ports for 5 v tolerant* 1 )v in ?0.3 to +6.5 v reference power supply voltage vrefh0 ?0.3 to avcc0 + 0.3 v vrefh analog power supply voltage avcc0 ?0.3 to +4.6 v analog input voltage v an ?0.3 to avcc0 + 0.3 (when an000 to an007 and an021 used) ?0.3 to vcc + 0.3 (when an008 to an015 used) v lcd voltage v l1 voltage v l1 ?0.3 to +2.8 v v l2 voltage v l2 ?0.3 to +6.5 v l3 voltage v l3 ?0.3 to +6.5 v l4 voltage v l4 ?0.3 to +6.5 operating temperature* 2 t opr ?40 to +85 ?40 to +105 c storage temperature t stg ?55 to +125 c table 5.2 recommended operating conditions item symbol conditions min. typ. max. unit power supply voltages vcc when usb not used 1.8 ? 3.6 v when usb used 3.0 ? 3.6 vss ? 0 ? usb power supply voltages vcc_usb ? vcc ? v vss_usb ? 0 ? analog power supply voltages avcc0 *1, *2 1.8 ? 3.6 v avss0 ? 0 ?
r01ds0216ej0102 rev.1.02 page 54 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.2 dc characteristics note 1. there are restrictions on avcc0 and vcc depending on the usage conditions for the 12-bit d/a converter and i/o ports. when using ports j0 and j2 multiplexed with da0 and da1 as general i/o ports, make sure that vcc avcc0. table 5.3 dc characteristics (1) conditions: vcc = vcc_usb = 2.7 to 3.6 v, avcc0 = 2.7 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus, 5 v tolerant) v ih vcc 0.7 ? 5.8 v ports 16, 17, port a6, port b0 (5 v tolerant) vcc 0.8 ? 5.8 other pins ports 02, 04, 07, ports 10 to 15 ports 20 to 27, ports 30 to 32, 35 ports 50 to 56, ports a0 to a7 ports b0 to b7 ports c0 to c7 ports d0 to d4 ports e0 to e7 ports f6, f7 port h7, res# ports j0, j2, j3* 1 vcc 0.8 ? vcc + 0.3 riic input pin (except for smbus) v il ?0.3 ? vcc 0.3 other than riic input pin ?0.3 ? vcc 0.2 riic input pin (except for smbus) ? v t vcc 0.05 ? ? other than riic input pin vcc 0.1 ? ? input voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v xtal (external clock input) vcc 0.8 ? vcc + 0.3 ports 40 to 44, 46, ports j6, j7, ports 90 to 92 avcc0 0.7 ? avcc0 + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 md v il ?0.3 ? vcc 0.1 xtal (external clock input) ?0.3 ? vcc 0.2 ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ?0.3 ? avcc0 0.3 riic input pin (smbus) ?0.3 ? 0.8
r01ds0216ej0102 rev.1.02 page 55 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. there are restrictions on avcc0 and vcc depending on the usage conditions for the 12-bit d/a converter and i/o ports. when using ports j0 and j2 multiplexed with da0 and da1 as general i/o ports, make sure that vcc avcc0. table 5.4 dc characteristics (2) conditions: vcc = vcc_usb = 1.8 to 2.7 v, avcc0 = 1.8 to 2.7 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage ports 16, 17, port a6, port b0 (5 v tolerant) v ih vcc 0.8 ? 5.8 v other pins ports 02, 04, 07, ports 10 to 15 ports 20 to 27, ports 30 to 32, 35 ports 50 to 56, ports a0 to a7 ports b0 to b7 ports c0 to c7 ports d0 to d4 ports e0 to e7 ports f6, f7 port h7, res# ports j0, j2, j3* 1 vcc 0.8 ? vcc + 0.3 all pins v il ?0.3 ? vcc 0.2 all pins ? v t vcc 0.01 ? ? input voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v xtal (external clock input) vcc 0.8 ? vcc + 0.3 ports 40 to 44, 46, ports j6, j7, ports 90 to 92 avcc0 0.7 ? avcc0 + 0.3 md v il ?0.3 ? vcc 0.1 xtal (external clock input) ?0.3 ? vcc 0.2 ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ?0.3 ? avcc0 0.3 table 5.5 dc characteristics (3) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input leakage current res#, md, port 35 port h7 ? i in ? ??1.0av in = 0 v, vcc three-state leakage current (off-state) ports for 5 v tolerant ? i tsi ? ??1.0av in = 0 v, 5.8 v pins other than above ? ? 1.0 v in = 0 v, vcc input capacitance all input pins (except for port 35, port 16, usb0_dm, usb0_dp) c in ? ? 15 pf v in = 0 v frequency: 1 mhz t a = 25c port 35, port 16, usb0_dm, usb0_dp ? ? 30 table 5.6 dc characteristics (4) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input pull-up resistor all ports (except for ports 35, ph7) r u 10 20 100 k ? v in = 0 v
r01ds0216ej0102 rev.1.02 page 56 of 121 dec 01, 2014 rx113 group 5. electrical characteristics table 5.7 dc characteristics (5) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol typ * 4 max unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 32 mhz i cc 3.6 ? ma iclk = 16 mhz 2.4 ? iclk = 8 mhz 1.8 ? all peripheral operation: normal* 3 iclk = 32 mhz 14.0 ? iclk = 16 mhz 7.9 ? iclk = 8 mhz 4.9 ? all peripheral operation: max.* 3 iclk = 32 mhz ? 30.0 sleep mode no peripheral operation* 2 iclk = 32 mhz 1.9 ? iclk = 16 mhz 1.5 ? iclk = 8 mhz 1.3 ? all peripheral operation: normal* 3 iclk = 32 mhz 8.2 ? iclk = 16 mhz 4.8 ? iclk = 8 mhz 3.1 ? deep sleep mode no peripheral operation* 2 iclk = 32 mhz 1.1 ? iclk = 16 mhz 0.95 ? iclk = 8 mhz 0.86 ? all peripheral operation: normal* 3 iclk = 32 mhz 6.4 ? iclk = 16 mhz 3.8 ? iclk = 8 mhz 2.4 ? increase during bgo operation* 5 2.5 ? middle-speed operating modes normal operating mode no peripheral operation* 6 iclk = 12 mhz i cc 2.1 ? ma iclk = 8 mhz 1.4 ? iclk = 1 mhz 0.77 ? all peripheral operation: normal* 7 iclk = 12 mhz 6.3 ? iclk = 8 mhz 4.6 ? iclk = 1 mhz 1.6 ? all peripheral operation: max.* 7 iclk = 12 mhz ? 14.2 sleep mode no peripheral operation* 6 iclk = 12 mhz 1.4 ? iclk = 8 mhz 0.90 ? iclk = 1 mhz 0.68 ? all peripheral operation: normal* 7 iclk = 12 mhz 3.9 ? iclk = 8 mhz 2.9 ? iclk = 1 mhz 1.4 ? deep sleep mode no peripheral operation* 6 iclk = 12 mhz 1.1 ? iclk = 8 mhz 0.63 ? iclk = 1 mhz 0.55 ? all peripheral operation: normal* 7 iclk = 12 mhz 3.3 ? iclk = 8 mhz 2.4 ? iclk = 1 mhz 1.2 ? increase during bgo operation* 5 2.5 ?
r01ds0216ej0102 rev.1.02 page 57 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. supply current values do not include output charge/discharge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functi ons is stopped. this does not include bgo operation. the clock source is pll. fclk and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operation. the clock source is pll. fclk and pclk are set to the same frequency as iclk. note 4. values when vcc = 3.3 v. note 5. this is the increase for programming or erasure of the rom or e2 dataflash during program execution. note 6. clock supply to the peripheral functions is stopped. the clock source is pll when iclk = 12 mhz, and hoco otherwise. fcl k and pclk are set to divided by 64. note 7. clocks are supplied to the peripheral functions. the clock source is pll when iclk = 12 mhz, and hoco otherwise. fclk an d pclk are set to the same frequency as iclk. note 8. clock supply to the peripheral functions is stopped. the clock source is the sub-clock oscillator. fclk and pclk are set to divided by 64. note 9. clocks are supplied to the peripheral functions. the clock source is the sub-cl ock oscillator. fclk and pclk are set to the same frequency as iclk. note 10. values when the mstpcra.mstpa17 bit (12-bit a/d converter mo dule stop bit) is set to ?transition to the module stop sta te is made?. figure 5.1 voltage dependency in high-speed operating mode (reference data) supply current* 1 low-speed operating mode normal operating mode no peripheral operation* 8 iclk = 32.768 khz i cc 4.3 ? a all peripheral operation: normal* 9, * 10 iclk = 32.768 khz 15.0 ? all peripheral operation: max.* 9, * 10 iclk = 32.768khz ? 62 sleep mode no peripheral operation* 8 iclk = 32.768 khz 2.3 ? all peripheral operation: normal* 9 iclk = 32.768 khz 8.6 ? deep sleep mode no peripheral operation* 8 iclk = 32.768 khz 1.7 ? all peripheral operation: normal* 9 iclk = 32.768 khz 7.0 ? item symbol typ * 4 max unit test conditions 0 5 10 15 20 25 1.5 2.0 2.5 3.0 3.5 4.0 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) i cc (ma) t a = 85/105c, iclk = 32 mhz *2 t a = 25c, iclk = 32 mhz *1 t a = 25c, iclk = 16 mhz *1 t a = 25c, iclk = 8 mhz *1 t a = 85/105c, iclk = 16 mhz *2 t a = 85/105c, iclk = 8 mhz *2
r01ds0216ej0102 rev.1.02 page 58 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.2 voltage dependency in middle -speed operating mode (reference data) figure 5.3 voltage dependency in low-speed operating mode (reference data) 0 2 4 6 8 10 12 1.5 2.0 2.5 3.0 3.5 4.0 t a = 85/105c, iclk = 12 mhz *2 t a = 25c, iclk = 8 mhz *1 t a = 85/105c, iclk = 8 mhz *2 t a = 85/105c, iclk = 1 mhz *2 t a = 25c, iclk = 1 mhz *1 t a = 25c, iclk = 12 mhz *1 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. vcc (v) i cc (ma) 0 10 20 30 40 50 60 1.5 2.0 2.5 3.0 3.5 4.0 t a = 105c, iclk = 32 khz *2 t a = 25c, iclk = 32 khz *1 t a = 85c, iclk = 32 khz *2 note 1. all peripheral operation is normal. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. average value of the tested upper-limit samples during product evaluation. vcc (v) i cc ( a)
r01ds0216ej0102 rev.1.02 page 59 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. supply current values do not include output charge/discharge current from all pins. the values appl y when internal pull- up moss are in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. note 4. includes the oscillation circuit. figure 5.4 voltage dependency in software standby mode (reference data) table 5.8 dc characteristics (6) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 t a = 25c i cc 0.44 0.98 a t a = 55c 0.80 3.47 t a = 85c 2.7 12.0 t a = 105c 6.17 42.7 increment for rtc operation* 4 0.31 ? rcr3.rtcdv[2:0] = 010b 1.09 ? rcr3.rtcdv[2:0] = 100b note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 0.1 1 10 100 1.5 2 2.5 3 3.5 4 t a = 105c *2 t a = 85c *2 t a = 105c *1 t a = 85c *1 t a = 55c *2 t a = 55c *1 t a = 25c *2 t a = 25c *1
r01ds0216ej0102 rev.1.02 page 60 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.5 temperature dependency in software standby mode (reference data) note: make sure that tj < t a + 0.1 * total power consumption (mw), where total power consumption = (vcc - v oh ) i oh + v ol i ol + i cc max vcc. note: make sure that tj < ta + 0.1 * total power consumption (mw), where total power consumption = (vcc - v oh ) i oh + v ol i ol + i cc max vcc. table 5.9 dc characteristics (7) conditions: products with operating temperature (t a ) ?40 to +105c vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v item symbol typ. max. unit test conditions permissible junction temperature tj ? 120 c high-speed operating mode ? 105 middle-speed operating mode ? 120 low-speed operating mode table 5.10 dc characteristics (8) conditions: products with operating temperature (t a ) ?40 to +85c vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v item symbol typ. max. unit test conditions permissible junction temperature tj ? 120 c high-speed operating mode ? 105 middle-speed operating mode ? 120 low-speed operating mode note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. 0.1 1 10 100 ?40?200 20406080100120 *2 *1
r01ds0216ej0102 rev.1.02 page 61 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. current consumed only by the usb module. note 2. includes the current supplied from the pull-up resistor of the usb0_dp pin to the pull-down resistor of the host device, in addition to the current consumed by this mcu during the suspended state. note 3. current consumed by the power supplies (vcc and usb_vcc). note 4. current consumed only by the comparator b module. note 5. current consumed only by the lcd modul e. current when the lcd panel is not connected. note 6. current consumed by the power supply (vcc). note 7. when vcc = avcc0 = vcc_usb = 3.3 v. note 8. it does not include the current that flows through external divider resistors. table 5.11 dc characteristics (9) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ.* 7 max. unit test conditions analog power supply current during a/d conversion (at high-speed conversion) i avcc ?0.71.2ma during d/a conversion (per channel) ? 0.4 0.8 waiting for a/d and d/a conversion (all units) ? ? 0.4 a reference power supply current during a/d conversion (at high-speed conversion) i refh0 ?2552 a waiting for a/d conversion (all units) ? ? 60 na during d/a conversion i refh ? 50 100 a waiting for d/a conversion (all units) ? ? 100 na temperature sensor* 6 ?i temp ?75 ? a comparator b operating current* 6 window mode i cmp * 4 ? 12.5 ? a comparator high-speed mode ? 6.5 ? a comparator low-speed mode ? 1.7 ? a lcd operating current* 6 external resistance division method* 8 f lcd = f sub = 128 hz, 1/3 bias, and 4-time slice i lcd1 * 5 ?0.04 ? a internal voltage boosting method (vlcd.vlcd = 04) f lcd = f sub = 128 hz, 1/3 bias, and 4-time slice i lcd2 * 5 ?0.85 ? a internal voltage boosting method (vlcd.vlcd = 12) f lcd = f sub = 128 hz, 1/3 bias, and 4-time slice i lcd2 * 5 ?1.55 ? a capacitor split method f lcd = f sub = 128 hz, 1/3 bias, and 4-time slice i lcd3 * 5 ?0.20 ? a usb operating current* 3 during usb communication operation under the following settings and conditions ? host controller operation is set to full-speed mode bulk out transfer (64 bytes) 1, bulk in transfer (64 bytes) 1 ? connect peripheral devices via a 1-meter usb cable from the usb port. i usbh * 1 ?4.3 (vcc) 0.9 (vcc_usb)* 3 ?ma during usb communication operation under the following settings and conditions ? function controller operation is set to full-speed mode bulk out transfer (64 bytes) 1, bulk in transfer (64 bytes) 1 ? connect the host device via a 1-meter usb cable from the usb port. i usbf * 1 ?3.6 (vcc) 1.1 (vcc_usb)* 3 ?ma during suspended state under the following setting and conditions ? function controller operation is set to full-speed mode (pull up the usb0_dp pin) ? software standby mode ? connect the host device via a 1-meter usb cable from the usb port. i susp * 2 ?0.35 (vcc) 170 (vcc_usb)* 3 ? a
r01ds0216ej0102 rev.1.02 page 62 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. when ofs1.(stuplvd1ren, faststup) = 11b. note 2. when ofs1.(stuplvd1ren, faststup) = 10b. note 3. when ofs1.stuplvd1ren = 0. note 4. turn on the power supply voltage according to the normal startup rising gradient because the register settings set by of s1 are not read in boot mode. figure 5.6 ripple waveform table 5.12 dc characteristics (10) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions ram standby voltage v ram 1.8 ? 3.6 v table 5.13 dc characteristics (11) conditions: vcc = avcc0 = vcc_usb = 0 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions power-on vcc rising gradient at normal startup* 1 srvcc 0.02 ? 20 ms/v during fast startup time* 2 0.02 ? 2 voltage monitoring 1 reset enabled at startup * 3, * 4 0.02 ? ? table 5.14 dc characteristics (12) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c the ripple voltage must meet the allowable ripple frequency f r(vcc) within the range between the vcc upper limit (3.6 v) and lower limit (1.8 v). when vcc change exceeds vcc 10%, the allowable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r (vcc) ? ? 10 khz figure 5.6 v r (vcc) vcc 0.2 ? ? 1 mhz figure 5.6 v r (vcc) vcc 0.08 ? ? 10 mhz figure 5.6 v r (vcc) vcc 0.06 allowable voltage change rising/ falling gradient dt/dvcc 1.0 ? ? ms/v when vcc change exceeds vcc 10% v r(vcc) vcc 1/f r(vcc)
r01ds0216ej0102 rev.1.02 page 63 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note: the recommended capacitance is 4.7 f. variations in connected capacitor s should be within the above range. note: do not exceed the permissible total supply current. table 5.15 dc characteristics (13) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions permissible error of vcl pin external capacitance c vcl 1.4 4.7 7.0 f table 5.16 permissible output currents conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol max. unit permissible output low current (average value per pin) ports 40 to 44, 46, ports j6, j7, ports 90 to 92 i ol 0.4 ma ports other than above 8.0 permissible output low current (maximum value per pin) ports 40 to 44, 46, ports j6, j7, ports 90 to 92 0.4 ports other than above 8.0 permissible output low current total of ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ? i ol 2.4 total of ports 02, 04, 07, p20 to 27, p30, p31, pj0, pj2, pj3 30 total of ports 10 to 17, ports 32, ports 50 to 56 ports c0 to c7, ports b0 to b7 30 total of ports e0 to e7, ports a0 to a7, ports f6, 7, ports d0 to d4 30 total of all output pins 60 permissible output high current (average value per pin) ports 40 to 44, 46, ports j6, j7, ports 90 to 92 i oh ?0.1 ports other than above ?4.0 permissible output high current (maximum value per pin) ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ?0.1 ports other than above ?4.0 permissible output high current total of ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ? i oh ?0.6 total of ports 02, 04, 07, p20 to 27, p30, p31, pj0, pj2, pj3 ?10 total of ports 10 to 17, ports 32, ports 50 to 56, ports c0 to c7, ports b0 to b7 ?15 total of ports e0 to e7, ports a0 to a7, ports f6, 7, ports d0 to d4 ?15 total of all output pins ?40
r01ds0216ej0102 rev.1.02 page 64 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. there are restrictions on avcc0 and vcc depending on the usage conditions for the 12-bi t d/a converter and i/o ports. when using ports j0 and j2 multiplexed with da0 and da1 as general i/o ports, make sure that vcc avcc0. note 1. there are restrictions on avcc0 and vcc depending on the usage conditions for the 12-bi t d/a converter and i/o ports. when using ports j0 and j2 multiplexed with da0 and da1 as general i/o ports, make sure that vcc avcc0. table 5.17 output valu es of voltage (1) conditions: vcc = vcc_usb = 2.7 to 3.6 v, avcc0 = 2.7 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions low-level output voltage all output ports (except for riic, port 4, port 9, and port j) v ol ?0 . 6vi ol = 3.0 ma ?0 . 4 i ol = 1.5 ma ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ? 0.4 i ol = 0.4 ma riic pins standard mode ? 0.4 i ol = 3.0 ma fast mode ? 0.6 i ol = 6.0 ma high-level output voltage all output ports (except for port 4, port 9, and port j)* 1 v oh vcc ? 0.5 ? v i oh = ?2.0 ma ports 40 to 44, 46, ports j6, j7, ports 90 to 92 avcc0 ? 0.5 ? i oh = ?0.1 ma table 5.18 output valu es of voltage (2) conditions: vcc = vcc_usb = 1.8 to 2.7 v, avcc0 = 1.8 to 2.7 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions low-level output voltage all output ports (except for port 4, port 9, and port j) v ol ?0 . 6vi ol = 1.5 ma ports 40 to 44, 46, ports j6, j7, ports 90 to 92 ? 0.4 i ol = 0.4 ma high-level output voltage all output ports (except for port 4, port 9, and port j)* 1 v oh vcc ? 0.5 ? v i oh = ?1.0 ma ports 40 to 44, 46, ports j6, j7, ports 90 to 92 avcc0 ? 0.5 ? i oh = ?0.1 ma
r01ds0216ej0102 rev.1.02 page 65 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.2.1 standard i/o pin outp ut characteristics (1) figure 5.7 to figure 5.10 show the characteristics of general ports (excep t for the riic output pin, ports 4, j6, j7, and 9). figure 5.7 v oh /v ol and i oh /i ol voltage characteristics of general ports (except for riic output pin, ports 4, j6, j7, and 9) at t a = 25c (reference data) figure 5.8 v oh /v ol and i oh /i ol temperature characteristics of general ports (except for riic output pin, ports 4, j6, j7, and 9) at vcc = 1.8 v (reference data) ?30 ?20 ?10 0 10 20 30 40 0 0.5 1 1.5 2 2.5 3 3.5 v oh /v ol [v] i oh /i ol vs v oh /v ol vcc = 3.3 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 1.8 v vcc = 1.8 v i oh /i ol [ma] ?6 ?4 ?2 0 2 4 6 8 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v oh /v ol [v] i oh /i ol vs v oh /v ol t a = ?40c t a = ?40c t a = 25c t a = 25c t a = 105c t a = 105c i oh /i ol [ma]
r01ds0216ej0102 rev.1.02 page 66 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.9 v oh /v ol and i oh /i ol temperature characteristics of general ports (except for riic output pin, ports 4, j6, j7, and 9) at vcc = 2.7 v (reference data) figure 5.10 v oh /v ol and i oh /i ol temperature characteristics of general ports (except for riic output pin, ports 4, j6, j7, and 9) at vcc = 3.3 v (reference data) i oh /i ol [ma] ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 v oh /v ol [v] i oh /i ol vs v oh /v ol t a = ? 40 c t a = ? 40 c t a = 25c t a = 25c t a = 105c t a = 105c ?30 ?20 ?10 0 10 20 30 40 50 0 0.5 1 1.5 2 2.5 3 3.5 4 v oh /v ol [v] i oh /i ol vs v oh /v ol t a = ?40c t a = ?40c t a = 25c t a = 25c t a = 105c t a = 105c i oh /i ol [ma]
r01ds0216ej0102 rev.1.02 page 67 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.2.2 standard i/o pin outp ut characteristics (2) figure 5.11 to figure 5.13 show the characteristics of the riic output pin. figure 5.11 v ol and i ol voltage characteristics of riic output pin at t a = 25c (reference data) figure 5.12 v ol and i ol temperature characteristics of riic output pin at vcc = 2.7 v (reference data) 0 5 10 15 20 25 30 35 40 00.511.522.5 3 3.5 v oh /v ol [v] i ol vs v ol vcc = 3.3 v vcc = 2.7 v i ol [ma] 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 v ol [v] i ol vs v ol t a = ?40c t a = 25c t a = 105c i ol [ma]
r01ds0216ej0102 rev.1.02 page 68 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.13 v ol and i ol temperature characteristics of riic output pin at vcc = 3.3 v (reference data) 0 5 10 15 20 25 30 35 40 45 50 0 0.5 1 1.5 2 2.5 3 3.5 4 v ol [v] i ol vs v ol t a = ?40c t a = 25c t a = 105c i ol [ma]
r01ds0216ej0102 rev.1.02 page 69 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.2.3 standard i/o pin outp ut characteristics (3) figure 5.14 to figure 5.17 show the characteristics of ports 4, j6, j7, and 9. figure 5.14 v oh /v ol and i oh /i ol voltage characteristics of ports 4, j6, j7, and 9 at t a = 25c (reference data) figure 5.15 v oh /v ol and i oh /i ol temperature characteristics of ports 4, j6, j7, and 9 at vcc = 1.8 v (reference data) ?4 ?2 0 2 4 6 8 10 12 14 0 0.5 1 1.5 2 2.5 3 3.5 v oh /v ol [v] i oh /i ol vs v oh /v ol vcc = 3.3 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 1.8 v vcc = 1.8 v i oh /i ol [ma] ?1 ?1 0 1 1 2 2 3 3 4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v oh /v ol [v] i oh /i ol vs v oh /v ol t a = ?40c t a = ?40c t a = 25c t a = 25c t a = 105c t a = 105c i oh /i ol [ma]
r01ds0216ej0102 rev.1.02 page 70 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.16 v oh /v ol and i oh /i ol temperature characteristics of ports 4, j6, j7, and 9 at vcc = 2.7 v (reference data) figure 5.17 v oh /v ol and i oh /i ol temperature characteristics of ports 4, j6, j7, and 9 at vcc = 3.3 v (reference data) ?4 ?2 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 v oh /v ol [v] i oh /i ol vs v oh /v ol t a = ?40c t a = ?40c t a = 25c t a = 25c t a = 105c t a = 105c i oh /i ol [ma] ?4 ?2 0 2 4 6 8 10 12 14 16 0 0.5 1 1.5 2 2.5 3 3.5 4 v oh /v ol [v] i oh /i ol vs v oh /v ol t a = ?40c t a = ?40c t a = 25c t a = 25c t a = 105c t a = 105c i oh /i ol [ma]
r01ds0216ej0102 rev.1.02 page 71 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.3 ac characteristics 5.3.1 clock timing note 1. the lower-limit frequency of fclk is 1 mhz during progra mming or erasing of the flash me mory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5 %. confirm the frequency accuracy of the clock source. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the a/d converter is in use. note 4. the vcc_usb range is 3.0 to 3.6 v when the usb clock is in use. note 1. the lower-limit frequency of fclk is 1 mhz during progra mming or erasing of the flash me mory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the a/d converter is in use. note 4. the vcc_usb range is 3.0 to 3.6 v when the usb clock is in use. note 1. programming and erasing t he flash memory is impossible. note 2. the a/d converter cannot be used. table 5.19 operation frequency value (high-speed operating mode) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol vcc unit 1.8 to 2.4 v 2.4 to 2.7 v 2.7 to 3.6 v when usb in use* 4 maximum operating frequency system clock (iclk) f max 81 63 23 2m h z flashif clock (fclk)* 1, * 2 81 63 23 2 peripheral module clock (pclkb) 8 16 32 32 peripheral module clock (pclkd)* 3 81 63 23 2 usb clock (uclk) f usb ??? 4 8 table 5.20 operation frequency value (middle-speed operating mode) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol vcc unit 1.8 to 2.4 v 2.4 to 2.7 v 2.7 to 3.6 v when usb in use* 4 maximum operating frequency system clock (iclk) f max 81 21 21 2m h z flashif clock (fclk)* 1, * 2 81 21 21 2 peripheral module clock (pclkb) 8 12 12 12 peripheral module clock (pclkd)* 3 81 21 21 2 usb clock (uclk) f usb ??? 4 8 table 5.21 operation frequency value (low-speed operating mode) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol vcc unit 1.8 to 2.4 v 2.4 to 2.7 v 2.7 to 3.6 v maximum operating frequency system clock (iclk) f max 32.768 khz flashif clock (fclk)* 1 32.768 peripheral module clock (pclkb) 32.768 peripheral module clock (pclkd)* 2 32.768
r01ds0216ej0102 rev.1.02 page 72 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. time until the clock can be used afte r the main clock oscillator stop bit (moscc r.mostp) is set to 0 (operating) when th e external clock is stable. note 2. reference values when an 8-mhz resonator is used. when specifying the main clock oscillator st abilization time, set the moscwtcr register with a stabilization time value that is equal to or greater than the resonator-manufacturer-recommended value. after changing the setting of the mosccr.mostp bit so that the main clock oscillator operates, read the oscovfsr.moovf flag to confirm that is has become 1, and then start using the main clock. note 3. the vcc range should be 2.4 to 3.6 v when the pll is used. note 4. after changing the setting of the sosccr.sostp bit or rcr3.r tcen bit so that the sub-clo ck oscillator operates, only sta rt using the sub-clock after the sub-clock oscillation stabilization wait ti me that is equal to or greater than the oscillator-manufacturer-recommended value has elapsed. reference value when a 32.768-khz resonator is used. note 5. the vcc range should be 3.0 to 3.6 v when the usbpll is used. note 6. the input frequency can be set to 6 or 8 mhz on ly and the oscillation frequency can be set to 48 mhz only. note 7. only 32.768 khz can be used. table 5.22 clock timing conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions xtal external clock input cycle time t xcyc 50 ? ? ns figure 5.18 xtal external clock input high pulse width t xh 20 ? ? ns xtal external clock input low pulse width t xl 20 ? ? ns xtal external clock rising time t xr ?? 5 ns xtal external clock falling time t xf ?? 5 ns xtal external clock input wait time* 1 t exwt 0.5 ? ? s main clock oscill ator oscillation frequency* 2 2.4 vcc 3.6 f main 1?20mhz 1.8 vcc < 2.4 1 ? 8 main clock oscillation st abilization time (crystal)* 2 t mainosc ? 3 ? ms figure 5.19 main clock oscillation st abilization time (ceramic resonator)* 2 t mainosc ?50? s loco clock oscillation frequency f loco 3.44 4.0 4.56 mhz loco clock oscillati on stabilization time t loco ??0.5 s figure 5.20 iwdt-dedicated clock oscillation frequency f iloco 12.75 15 17.25 khz iwdt-dedicated clock oscilla tion stabilization time t iloco ??50 s figure 5.21 hoco clock oscillation frequency f hoco 31.52 32 32.48 mhz t a = ?40 to 85c 31.68 32 32.32 t a = ?20 to 85c 31.36 32 32.64 t a = ?40 to 105c hoco clock oscillati on stabilization time t hoco ??56 s figure 5.23 pll input frequency* 3 f pllin 4?8mhz pll circuit oscillation frequency* 3 f pll 32 ? 48 mhz pll clock oscillation stabilization time t pll ??50 s figure 5.24 pll free-running oscillation frequency f pllfr ?8?mhz usbpll input frequency* 5 f pllin ?6, 8* 6 ?mhz usbpll circuit oscillation frequency* 5 f pll ? 48* 6 ?mhz usbpll clock oscillation stabilization time t pll ??50 s figure 5.24 sub-clock oscillator oscillation frequency* 7 f sub ? 32.768 ? khz sub-clock oscillation stabilization time* 4 t subosc ? 0.5 ? s figure 5.25
r01ds0216ej0102 rev.1.02 page 73 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.18 xtal external clock input timing figure 5.19 main clock oscillation start timing figure 5.20 loco clock oscillation start timing figure 5.21 iwdt-dedicated clock oscillation start timing t xh t xcyc xtal external clock input vcc 0.5 t xl t xr t xf main clock oscillator output mosccr.mostp t mainosc loco clock oscillator output lococr.lcstp t loco iwdt-dedicated clock oscillator output ilococr.ilcstp t iloco
r01ds0216ej0102 rev.1.02 page 74 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.22 hoco clock oscillation start timi ng (after reset is canceled by setting ofs1.hocoen bit to 0) figure 5.23 hoco clock oscillati on start timing (oscillation is started by setting hococr.hcstp bit) figure 5.24 pll clock oscillation start timing (pll is operated after main clock oscillation has settled) figure 5.25 sub-clock oscillation start timing res# internal reset hoco clock ofs1.hocoen t reswt hoco clock hococr.hcstp t hoco pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output t pll sub-clock oscillator output sosccr.sostp t subosc
r01ds0216ej0102 rev.1.02 page 75 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.3.2 reset timing note 1. when ofs1.(stuplvd1ren, faststup) = 11b. note 2. when ofs1.(stuplvd1ren, faststup) 11b. note 3. when iwdtcr.cks[3:0] = 0000b. figure 5.26 reset input timing at power-on figure 5.27 reset input timing (1) figure 5.28 reset input timing (2) table 5.23 reset timing conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions res# pulse width at power-on t reswp 3 ? ? ms figure 5.26 other than above t resw 30 ? ? s figure 5.27 wait time after res# cancellation (at power-on) at normal startup* 1 t reswt ? 8.5 ? ms figure 5.26 during fast startup time* 2 t reswt ? 560 ? s wait time after res# cancellation (during powered-on state) t reswt ?114? s figure 5.27 independent watchdog timer reset period t reswiw ?1?iwdt clock cycle figure 5.28 software reset period t reswsw ?1?iclk cycle wait time after independent watchdog timer reset cancellation* 3 t resw2 ? 300 ? s wait time after software reset cancellation t resw2 ? 168 ? s vcc res# t reswp internal reset t reswt res# internal reset t reswt t resw independent watchdog timer reset software reset internal reset t reswt2 t reswiw, t reswsw
r01ds0216ej0102 rev.1.02 page 76 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note 1. the recovery time varies depending on the state of each oscillator when the wait instruction is executed. the recovery t ime when multiple oscillators are operating varies depending on the oper ating state of the oscillators that are not selected as the system clock source. this applies when only the oscillator listed in each item is operating and the other oscillators are stopp ed. note 2. when the frequency of the crystal is 20 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 3. when the frequency of pll is 32 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 4. when the frequency of the external clock is 20 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 5. when the frequency of pll is 32 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 6. when the frequency of hoco is 32 mhz. when the high-speed clock oscillator wait control register (hocowtcr) is set to 05h. note 1. the recovery time varies depending on the state of each oscillator when the wait instruction is executed. the recovery t ime when multiple oscillators are operating varies depending on the oper ating state of the oscillators that are not selected as the system clock source. this applies when only the oscillator listed in each item is operating and the other oscillators are stopp ed. note 2. when the frequency of the crystal is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 3. when the frequency of pll is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 4. when the frequency of the external clock is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 5. when the frequency of pll is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 6. when the frequency of hoco is 8 mhz. when the high-speed clock oscillator wait control register (hocowtcr) is set to 05h. table 5.24 timing of recovery from low power consumption modes (1) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 high-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.29 main clock oscillator and pll circuit operating* 3 t sbypc ?2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex ?3550 s main clock oscillator and pll circuit operating* 5 t sbype ?7095 s sub-clock oscillator operating t sbysc ? 650 800 s hoco clock oscillator operating* 6 t sbyho ?4055 s loco clock oscillator operating t sbylo ?4055 s table 5.25 timing of recovery from low power consumption modes (2) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 middle-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.29 main clock oscillator and pll circuit operating* 3 t sbypc ?2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex ?3 4 s main clock oscillator and pll circuit operating* 5 t sbype ?6585 s sub-clock oscillator operating t sbysc ? 600 750 s hoco clock oscillator operating* 6 t sbyho ?4050 s loco clock oscillator operating t sbylo ?4.8 7 s
r01ds0216ej0102 rev.1.02 page 77 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. the sub-clock conti nues oscillating in software standby mode during low-speed mode. figure 5.29 software standby mode recovery timing table 5.26 timing of recovery from low power consumption modes (3) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* 1 low-speed mode sub-clock oscillator operating t sbysc ? 600 750 s figure 5.29 oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbyho, t sbylo
r01ds0216ej0102 rev.1.02 page 78 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. oscillators continue oscillating in deep sleep mode. note 2. when the frequency of the system clock is 32 mhz. note 3. when the frequency of the system clock is 12 mhz. note 4. when the frequency of the system clock is 32.768 khz. figure 5.30 deep sleep mode recovery timing note: when pclkb, pclkd, and fclk are set to the same frequency division ratio as iclk. table 5.27 timing of recovery from low power consumption modes (4) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from deep sleep mode* 1 high-speed mode* 2 t dslp ?23.5 s middle-speed mode* 3 t dslp ?3 4 s low-speed mode* 4 t dslp ? 400 500 s table 5.28 timing of recovery from low power consumption modes (5) operating mode transition time conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c mode before transition mode after transition iclk frequency transition time unit min. typ. max. high-speed operating mode middle-speed operating mode 8 mhz ? 10 ? s middle-speed operating mode high- speed operating mode 8 mhz ? 37.5 ? s low-speed operating mode middle-speed operating mode, high-speed operating mode 32.768 khz ? 213.62 ? s middle-speed operating mode, high-speed operating mode low-speed operating mode 32.768 khz ? 183.11 ? s oscillator iclk irq deep sleep mode t dslp
r01ds0216ej0102 rev.1.02 page 79 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.3.4 control signal timing note: 200 ns minimum in software standby mode. note 1. t pcyc indicates the cycle of pclkb. note 2. t nmick indicates the cycle of the nmi digital filter sampling clock. note 3. t irqck indicates the cycle of th e irqi digital filter samp ling clock (i = 0 to 7). figure 5.31 nmi interrupt input timing figure 5.32 irq interrupt input timing table 5.29 control signal timing conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns nmi digital filter disabled (nmiflte.nflten = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? nmi digital filter enabled (nmiflte.nflten = 1) t nmick 3 200 ns t nmick 3.5* 2 ?? t nmick 3 > 200 ns irq pulse width t irqw 200 ? ? ns irq digital filter disabled (irqflte0.flteni = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? irq digital filter enabled (irqflte0.flteni = 1) t irqck 3 200 ns t irqck 3.5* 3 ?? t irqck 3 > 200 ns nmi t nmiw irq t irqw
r01ds0216ej0102 rev.1.02 page 80 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.3.5 timing of on-chi p peripheral modules note 1. t pcyc : pclk cycle note 2. t cac : cac count clock source cycle note 3. when the loco is selected as the clock output source (c kocr.ckosel[2:0] bits = 000b), set the clock output division rati o selection to divided by 2 (ckocr.ckodiv[2:0] bits = 001b). note 4. when the xtal external clock input or an oscillator is used with divided by 1 (ckocr.ckosel[2:0] bits = 010b and ckocr.ckodiv[2:0] bits = 000b) to output from clkout, the abov e should be satisfied with an input duty cycle of 45 to 55%. table 5.30 timing of on-chi p peripheral modules (1) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit* 1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.33 mtu2 input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.34 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.35 both-edge setting 2.5 ? phase counting mode 2.5 ? poe poe# input pulse width t poew 1.5 ? t pcyc figure 5.36 tmr timer clock pulse width asynchronous t tmcwh , t tmcwl 1.5 ? t pcyc figure 5.37 clock synchronous 2.5 ? sci input clock cycle asynchronous t scyc 4?t pcyc figure 5.38 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?20ns input clock fall time t sckf ?20ns output clock cycle asynchronous t scyc 16 ? t pcyc figure 5.39 c = 30 pf clock synchronous 4 ? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?20ns output clock fall time t sckf ?20ns transmit data delay time (master) clock synchronous t txd ?40ns transmit data delay time (slave) clock synchronous 2.7 v or above ? 65 ns 1.8 v or above ? 100 ns receive data setup time (master) clock synchronous 2.7 v or above t rxs 65 ? ns 1.8 v or above 90 ? ns receive data setup time (slave) clock synchronous 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.40 cac cacref input pulse width t pcyc t cac * 2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac * 2 5 t cac + 6.5 t pcyc clkout clkout pin output cycle* 4 vcc = 2.7 v or above t ccyc 125 ? ns figure 5.41 vcc = 1.8 v or above 250 clkout pin high pulse width* 3 vcc = 2.7 v or above t ch 35 ? ns vcc = 1.8 v or above 70 clkout pin low pulse width* 3 vcc = 2.7 v or above t cl 35 ? ns vcc = 1.8 v or above 70 clkout pin output rise time vcc = 2.7 v or above t cr ?15ns vcc = 1.8 v or above 30 clkout pin output fall time vcc = 2.7 v or above t cf ?15ns vcc = 1.8 v or above 30
r01ds0216ej0102 rev.1.02 page 81 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. n: an integer from 1 to 8 that can be set by the rspi clock delay register (spckd) note 3. n: an integer from 1 to 8 that can be set by the rspi slave select negation delay register (sslnd) table 5.31 timing of on-chi p peripheral modules (2) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c, c = 30 pf item symbol min. max. unit test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc * 1 figure 5.42 slave 8 4096 rspck clock high pulse width master t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/fall time output 2.7 v or above t spckr , t spckf ?1 0n s 1.8 v or above ?1 5 input ?1 s data input setup time master 2.7 v or above t su 10 ? ns figure 5.43 to figure 5.48 1.8 v or above 30 ? slave 25 ? t pcyc ? data input hold time master rspck set to a division ratio other than pclkb divided by 2 t h t pcyc ?n s rspck set to pclkb divided by 2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead ?30 + n* 2 t spcyc ?n s slave 2?t pcyc ssl hold time master t lag ?30 + n* 3 t spcyc ?n s slave 2?t pcyc data output delay time master 2.7 v or above t od ?1 4n s 1.8 v or above ?3 0 slave 2.7 v or above ?3 t pcyc + 65 1.8 v or above ?3 t pcyc +105 data output hold time master 2.7 v or above t oh 0?n s 1.8 v or above ?20 ? slave 0? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/ fall time output 2.7 v or above t dr, t df ?1 0n s 1.8 v or above ?2 0 input ?1 s ssl rise/fall time output t sslr, tsslf ?2 0n s input ?1 s slave access time 2.7 v or above t sa ?6t pcyc figure 5.47, figure 5.48 1.8 v or above ?7 slave output release time 2.7 v or above t rel ?5t pcyc 1.8 v or above ?6
r01ds0216ej0102 rev.1.02 page 82 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note 1. t pcyc : pclk cycle table 5.32 timing of on-chi p peripheral modules (3) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c, c = 30 pf item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 5.42 sck clock cycle input (slave) 6 65536 t pcyc sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time (master) 2.7 v or above t su 65 ? ns figure 5.43, figure 5.45 1.8 v or above 95 ? data input setup time (slave) 40 ? data input hold time t h 40 ? ns ss input setup time t lead 3?t spcyc ss input hold time t lag 3?t spcyc data output delay time (master) t od ?40ns data output delay time (slave) 2.7 v or above ? 65 1.8 v or above ? 100 data output hold time (master) 2.7 v or above t oh ?10 ? ns 1.8 v or above ?20 ? data output hold time (slave) ?10 ? data rise/fall time t dr , t df ?20ns ss input rise/fall time t sslr , t sslf ?20ns slave access time t sa ?6t pcyc figure 5.47, figure 5.48 slave output release time t rel ?6t pcyc
r01ds0216ej0102 rev.1.02 page 83 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note: t iiccyc : riic internal reference count clock (iic ) cycle note 1. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the i cfer.nfe bit = 1. note 2. the minimum tsr and tsf specif ications for fast mode are not set. table 5.33 timing of on-chi p peripheral modules (4) conditions: vcc = avcc0 = vcc_usb = 2.7 to 3.6 v, vss = avss0 = vss_usb = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min.* 1 max. unit test conditions riic (standard mode, smbus) scl0 input cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.49 scl0 input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl0 input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl0, sda0 input rise time t sr ? 1000 ns scl0, sda0 input fall time t sf ? 300 ns scl0, sda0 input spike pulse removal time t sp 0 1 (4) t iiccyc ns sda0 input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns repeated start condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl0, sda0 capacitive load c b ? 400 pf riic (fast mode) scl0 input cycle time t scl 6 (12) t iiccyc + 600 ? ns figure 5.49 scl0 input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl0 input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl0, sda0 input rise time t sr ?* 2 300 ns scl0, sda0 input fall time t sf ?* 2 300 ns scl0, sda0 input spike pulse removal time t sp 0 1 (4) t iiccyc ns sda0 input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns repeated start condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl0, sda0 capacitive load c b ? 400 pf
r01ds0216ej0102 rev.1.02 page 84 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note: t pcyc : pclk cycle note 1. this applies when the smr.cks[1:0] bits = 00b and the snfr.nfcs[2:0] bits = 010b while the snfr.nfe bit = 1 and the digital filter is enabled. table 5.34 timing of on-chi p peripheral modules (5) conditions: vcc = avcc0 = vcc_usb = 2.7 to 3.6 v, vss = avss0 = vss_usb = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min. max. unit test conditions simple i 2 c (standard mode) sda0 input rise time t sr ? 1000 ns figure 5.49 sda0 input fall time t sf ? 300 ns sda0 input spike pulse removal time t sp 04 t pcyc * 1 ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl0, sda0 capacitive load c b ? 400 pf simple i 2 c (fast mode) scl0, sda0 input rise time t sr ? 300 ns figure 5.49 scl0, sda0 input fall time t sf ? 300 ns scl0, sda0 input spike pulse removal time t sp 04 t pcyc * 1 ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl0, sda0 capacitive load c b ? 400 pf table 5.35 timing of on-chi p peripheral modules (6) conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min. max. unit test conditions ssi audio_mclk input frequency 2.7 v or above t audio 12 5m h z 1.8 v or above 1 4 output clock cycle t o 250 ? ns figure 5.50 input clock cycle t i 250 ? ns clock high pulse width t hc 0.4 0.6 to, ti clock low pulse width t lc 0.4 0.6 to, ti clock rise time t rc ?2 0n s data delay time 2.7 v or above t dtr ? 65 ns figure 5.51 figure 5.52 1.8 v or above ? 105 setup time 2.7 v or above t sr 65 ? ns 1.8 v or above 90 ? hold time t htr 40 ? ns ws changing edge ssidata output delay t dtrw ? 105 ns figure 5.53
r01ds0216ej0102 rev.1.02 page 85 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.33 i/o port input timing figure 5.34 mtu2 input/output timing figure 5.35 mtu2 clock input timing figure 5.36 poe# input timing port pclk t prw output compare output input capture input pclk t ticw mtclka to mtclkd pclk t tckwl t tckwh poen# input pclk t poew
r01ds0216ej0102 rev.1.02 page 86 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.37 tmr clock input timing figure 5.38 sck clock input timing figure 5.39 sci input/output timing: clock synchronous mode pclk tmci0 to tmci3 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn n = 0, 1, 2, 5, 6, 8, 9, 12 t txd t rxs t rxh txdn rxdn sckn n = 0, 1, 2, 5, 6, 8, 9, 12
r01ds0216ej0102 rev.1.02 page 87 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.40 a/d converter external trigger input timing figure 5.41 clkout output timing figure 5.42 rspi clock timing and simple spi clock timing adtrg0# pclk t trgw t cf t ch t ccyc t cr t cl clkout pin output test conditions: v oh = vcc 0.7, v ol = vcc 0.3, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf sckn master select output sckn slave select input n = 0, 1, 2, 5, 6, 8, 9, 12 t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc rspcka master select output rspcka slave select input simple spi rspi
r01ds0216ej0102 rev.1.02 page 88 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.43 rspi timing (master, cpha = 0) (b it rate: pclkb set to division ratio other than divided by 2) and simple sp i timing (master, ckph = 1) figure 5.44 rspi timing (master, cpha = 0) (bit rate: pclkb set to divided by 2) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output n = 0, 1, 2, 5, 6, 8, 9, 12 simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output lsb in t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in msb out data lsb out idle msb out msb in data t hf
r01ds0216ej0102 rev.1.02 page 89 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.45 rspi timing (master, cpha = 1) (b it rate: pclkb set to division ratio other than divided by 2) and simple sp i timing (master, ckph = 0) figure 5.46 rspi timing (master, cpha = 1) (bit rate: pclkb set to divided by 2) ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od n = 0, 1, 2, 5, 6, 8, 9, 12 t dr, t df t hf t lead t td t lag t sslr, t sslf t oh data msb in msb out data lsb out idle msb out t od ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output msb in lsb in t su t h
r01ds0216ej0102 rev.1.02 page 90 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.47 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1) figure 5.48 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0) t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input n = 0, 1, 2, 5, 6, 8, 9, 12 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input n = 0, 1, 2, 5, 6, 8, 9, 12 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input
r01ds0216ej0102 rev.1.02 page 91 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.49 riic bus interface in put/output timing and simple i 2 c bus interface input/output timing figure 5.50 clock input/output timing figure 5.51 transmission/reception timing (synchronized with ssisckn rising edge) test conditions v ih = vcc 0.7, v il = vcc 0.3 sda0 scl0 v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respectively. s: start condition p: stop condition sr: repeated start condition ssisckn t hc t lc t rc t i , t o t sr t htr t dtr ssisckn (input or output) ssiwsn, ssidatan (input) ssiwsn, ssidatan (output)
r01ds0216ej0102 rev.1.02 page 92 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.52 transmission/reception timing (synchronized with ssisckn falling edge) figure 5.53 ssidata output de lay after ssiwsn changing edge t sr t htr t dtr ssisckn (input or output) ssiwsn, ssidatan (input) ssiwsn, ssidatan (output) t dtrw ssiwsn (input) ssidatan (output) note. timing to output the msb bit during slave transmission from ssiwsn when del = 1 and sdta = 0 or del = 1, sdta = 1, and swl[2:0] = dwl[2:0]
r01ds0216ej0102 rev.1.02 page 93 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.4 usb characteristics figure 5.54 usb0_dp and usb0_dm output timing table 5.36 usb characteristics (usb0_ dp and usb0_dm pin characteristics) conditions: vcc = avcc0 = vcc_usb = 3.0 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions input characteristics input high level voltage v ih 2.0 ? v input low level voltage v il ?0 . 8v differential input sensitivity v di 0.2 ? v | usb0_dp ? usb0_dm | differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 vcc_usb v i oh = ?200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross-over voltage v crs 1.3 2.0 v figure 5.54 figure 5.55 rise time fs t r 42 0n s ls 75 300 fall time fs t f 42 0n s ls 75 300 rise/fall time ratio fs t r /t f 90 111.11 % t r /t f ls 80 125 output resistance z drv 28 44 ? (adjusting the resistance of external elements is not necessary.) vbus characteristics vbus input voltage v ih vcc 0.8 ? v v il ?vcc 0.2v vbus (p16) input leakage current | i vbusin |? 10 a usb0_vbus = 5.5 v pull-up, pull-down pull-down resistor r pd 14.25 24.80 k ? pull-up resistor r pui 0.9 1.575 k ? during idle state r pua 1.425 3.09 k ? during reception battery charging specification ver 1.2 usb0_dp sink current i dp_sink 25 175 a usb0_dm sink current i dm_sink 25 175 a dcd source current i dp_src 71 3 a data detection voltage v dat_ref 0.25 0.4 v usb0_dp source current v dp_src 0.5 0.7 v output current = 250 a usb0_dm source current v dm_src 0.5 0.7 v output current = 250 a usb0_dp, usb0_dm t f t r 90% 10% 10% 90% v crs
r01ds0216ej0102 rev.1.02 page 94 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.55 test circuit observation point 50 pf 50 pf usb0_dp usb0_dm full-speed (fs) observation point 1.5 k 200 pf to 600 pf usb0_dp usb0_dm 200 pf to 600 pf 3.6 v observation point low-speed (ls)
r01ds0216ej0102 rev.1.02 page 95 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.5 a/d conversion characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. figure 5.56 avcc0 to avrefh0 voltage range table 5.37 a/d conversion characteristics (1) conditions: vcc = avcc0 = vrefh0 = 2.7 to 3.6 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 4 ? 32 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 32 mhz) permissible signal source impedance (max.) = 0.3 k ? 1.031 (0.313)* 2 ?? s high-precision channel adcsr.adhsc bit = 1 adsstrn.sst[7:0] bits = 09h 1.375 (0.641)* 2 ?? s normal-precision channel adcsr.adhsc bit = 1 adsstrn.sst[7:0] bits = 14h offset error ? 0.5 4.5 lsb high-precision channel pj6pfs.asel bit = 1 pj7pfs.asel bit = 1 6.0 lsb other than above full-scale error ? 0.75 4.5 lsb high-precision channel pj6pfs.asel bit = 1 pj7pfs.asel bit = 1 6.0 lsb other than above quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel pj6pfs.asel bit = 1 pj7pfs.asel bit = 1 8.0 lsb other than above dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 3.0 lsb 1.0 2.0 3.0 4.0 5.0 avcc0 1.0 2.0 3.0 4.0 5.0 avrefh0 1.8 1.8 2.7 3.6 2.4 2.4 2.7 3.6 characteristics listed in table 5.37 a/d conversion characteristics (1) characteristics listed in table 5.38 a/d conversion characteristics (2) characteristics listed in table 5.39 a/d conversion characteristics (3)
r01ds0216ej0102 rev.1.02 page 96 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. table 5.38 a/d conversion characteristics (2) conditions: vcc = avcc0 = vrefh0 = 2.4 to 2.7 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 4 ? 16 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 16 mhz) permissible signal source impedance (max.) = 1.0 k ? 2.062 (0.625)* 2 ?? s high-precision channel adcsr.adhsc bit = 1 adsstrn.sst[7:0] bits = 09h 2.750 (1.313)* 2 ?? s normal-precision channel adcsr.adhsc bit = 1 adsstrn.sst[7:0] bits = 14h offset error ? 0.5 6.0 lsb full-scale error ? 1.25 6.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 3.0 8.0 lsb dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.5 3.0 lsb table 5.39 a/d conversion characteristics (3) conditions: vcc = avcc0 = vrefh0 = 1.8 to 2.4 v, vss = avss0 = vrefl0 = vss_usb = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 8 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 8 mhz) permissible signal source impedance (max.) = 5.0 k ? 4.875 (1.250)* 2 ?? s high-precision channel adcsr.adhsc bit = 0 adsstrn.sst[7:0] bits = 09h 6.250 (2.625)* 2 ?? s normal-precision channel adcsr.adhsc bit = 0 adsstrn.sst[7:0] bits = 14h offset error ? 0.5 24.0 lsb full-scale error ? 1.25 24.0 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 2.75 32.0 lsb dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.25 12.0 lsb
r01ds0216ej0102 rev.1.02 page 97 of 121 dec 01, 2014 rx113 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diffe rential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time a nd the comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. note 1. the internal reference voltage cannot be selected for input channels when avcc0 < 2.0 v. note 2. the a/d internal reference voltage indicates the voltage wh en the internal reference voltage is input to the a/d convert er. table 5.40 a/d conversion characteristics (4) conditions: vcc = avcc0 = 2.0 to 3.6 v, vss = avss0 = vss_ usb = 0 v, adhvrefcnt.ocsvs el = 1 (internal reference voltage selected as high-side reference voltage), pj7pfs.asel = 0 (avss0 pin selected as low-side reference power supply ground pin) t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 2 mhz resolution ? ? 12 bit internal reference voltage 1.36 1.43 1.50 v conversion time* 1 (operation at pclkd = 2 mhz) permissible signal source impedance (max.) = 5.0 k ? 16 (1.5)* 2 ?? s high-precision channel adcsr.adhsc bit = 0 adsstrn.sst[7:0] bits = 02h 17.5 (3.0)* 2 ? ? normal-precision channel adcsr.adhsc bit = 0 adsstrn.sst[7:0] bits = 05h offset error ? ? 24.0 lsb dnl differential nonlinearity error ? 16.0 ? lsb inl integral nonlinearity error ? 16.0 32.0 lsb table 5.41 a/d converter channel classification classification channel conditions remarks high-precision channel an000 to an007, an021 avcc0 = 1.8 to 3.6 v pins an000 to an007 and an021 cannot be used as digital outputs when the a/d converter is in use. normal-precision channel an008 to an015 internal reference voltage input channel internal reference voltage avcc0 = 2.0 to 3.6 v temperature sensor input channel temperature sensor output avcc0 = 2.0 to 3.6 v table 5.42 a/d internal reference voltage characteristics conditions: vcc = avcc0 = vcc_usb = 2.0 to 3.6 v* 1 , vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions internal reference voltage input channel* 2 1.36 1.43 1.50 v
r01ds0216ej0102 rev.1.02 page 98 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.57 illustration of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0 = 3.072 v), then 1-lsb width becomes 0.75 mv, and 0 mv, 0.75 mv, 1.5 mv, ... are used as analog input voltages. if analog input voltage is 6 mv, absolute accuracy = 5 lsb means that the actual a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expect ed from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0216ej0102 rev.1.02 page 99 of 121 dec 01, 2014 rx113 group 5. electrical characteristics differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actual output code. offset error offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point of the ideal last output code and the actual last output code.
r01ds0216ej0102 rev.1.02 page 100 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.6 d/a conversion characteristics note 1. there are restrictions on avcc0 and vcc depending on the usage conditions for the 12-bi t d/a converter and i/o ports. when using ports j0 and j2 as da0 and da1 output, make sure that vcc d/a output voltage. note 1. there are restrictions on avcc0 and vcc depending on the usage conditions for the 12-bi t d/a converter and i/o ports. when using ports j0 and j2 as da0 and da1 output, make sure that vcc d/a output voltage. table 5.43 d/a conversion characteristics (1) conditions: vcc = avcc0 = vrefh = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vrefl = vss_usb = 0 v, t a = ?40 to +105c reference voltage = vrefh or vrefl selected item min. typ. max. unit test conditions resolution ? ? 12 bit resistive load 30 ? ? k ? capacitive load ? ? 50 pf output voltage range* 1 0.35 ? avcc0 - 0.47 v dnl differential nonlinearity error ? 0.5 1.0 lsb inl integral nonlinearity error ? 2.0 8.0 lsb offset error ? ? 20 mv full-scale error ? ? 20 mv output resistance ? 75 ? ? conversion time ? ? 30 s table 5.44 d/a conversion characteristics (2) conditions: vcc = avcc0 = vrefh = vcc_usb = 1.8 to 3.6v, vss = avss0 = vrefl = vss_usb = 0 v, t a = ?40 to +105c reference voltage = av cc0 or avss0 selected item min. typ. max. unit test conditions resolution ? ? 12 bit resistive load 30 ? ? k ? capacitive load ? ? 50 pf output voltage range* 1 0.35 ? avcc0 - 0.47 v dnl differential nonlinearity error ? 0.5 2.0 lsb inl integral nonlinearity error ? 2.0 8.0 lsb offset error ? ? 30 mv full-scale error ? ? 30 mv output resistance ? 75 ? ? conversion time ? ? 30 s
r01ds0216ej0102 rev.1.02 page 101 of 121 dec 01, 2014 rx113 group 5. electrical characteristics table 5.45 d/a conversion characteristics (3) conditions: vcc = avcc0 = vcc_usb = 2.0 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c reference voltage = internal reference voltage selected item min. typ. max. unit test conditions resolution ? ? 12 bit internal reference voltage (vbgr) 1.36 1.43 1.50 v resistive load 30 ? ? k ? capacitive load ? ? 50 pf output voltage range 0.35 ? vbgr v dnl differential nonlinearity error ? 2.0 16.0 lsb inl integral nonlinearity error ? 8.0 16.0 lsb offset error ? ? 30 mv output resistance ? 75 ? ? conversion time ? ? 30 s
r01ds0216ej0102 rev.1.02 page 102 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.58 illustration of d/a converter characteristic terms integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal output voltage based on the ideal conversion characteristic when the measured of fset and full-scale errors are zer oed, and the actual output voltage. differential nonlinearity error (dnl) differential nonlinearity erro r is the difference between 1-lsb voltage width based on the ideal d/a conversion characteristics and the width of the actual output voltage. offset error offset error is the difference between the highest actual output voltage that falls below the lower output limit and the ideal output voltage based on the input code. full-scale error full-scale error is the difference between the lowest actual output voltage that exceeds the upper ou tput limit and the ideal output voltage based on the input code. 000h d/a converter input code fffh output analog voltage upper output limit lower output limit offset error ideal output voltage 1-lsb width for ideal d/a conversion characteristic differential nonlinearity error (dnl) actual d/a conversion characteristic *1 integral nonlinearity error (inl) full-scale error gain error offset error ideal output voltage note 1. ideal d/a conversion output voltage that is adj usted so that offset and full scale errors are zeroed.
r01ds0216ej0102 rev.1.02 page 103 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.7 temperature sensor characteristics 5.8 comparator characteristics table 5.46 temperature sensor characteristics conditions: vcc = avcc0 = vcc_usb = 2.0 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions relative accuracy DD 1.5 D c 2.4 v or above D 2.0 D below 2.4 v temperature slope DD ?3.65 D mv/c output voltage (25c) DD 1.05 D v vcc = 3.3 v temperature sensor start time t start DD 5 s sampling time D 5 DD s table 5.47 comparator characteristics conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions cvrefb0 or cvrefb1 input reference voltage vref 0 ? vcc - 1.4 v cmpb0 or cmpb1 input voltage vi ?0.3 ? vcc + 0.3 v offset comparator high-speed mode ? ? ? 50 mv comparator high-speed mode window function enabled ?? ? 60mv comparator low-speed mode ? ? ? 40 mv comparator output delay time comparator high-speed mode td ? ? 1.2 svcc = 3 v, input slew rate 50 mv/us comparator high-speed mode window function enabled tdw ? ? 2 s comparator low-speed mode td ? ? 5 s high-side reference voltage (comparator high-speed mode, window function enabled) vrfh ? 0.76 vcc ? v low-side reference voltage (comparator high-speed mode, window function enabled) vrfl ? 0.24 vcc ? v operation stabilization wait time tcmp 100 ? ? s
r01ds0216ej0102 rev.1.02 page 104 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.59 comparator output delay time in comparator high-speed mode and low-speed mode figure 5.60 comparator output delay time in high-speed mode with window function enabled cmpb cmpob td td cvrefb = 0 v cmpb cmpob tdw tdw internal vrh = vcc * 0.76 cmpb cmpob tdw tdw internal vrh = vcc * 0.24
r01ds0216ej0102 rev.1.02 page 105 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.9 lcd characteristics 5.9.1 external resistance division method (1) static display mode (2) 1/2 bias method, 1/4 bias method (3) 1/3 bias method table 5.48 lcd characteristics conditions: vcc = avcc0 = vcc_usb = 2.0 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions lcd drive voltage v l4 2.0 D vcc v table 5.49 lcd characteristics conditions: vcc = avcc0 = vcc_usb = 2.7 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions lcd drive voltage v l4 2.7 D vcc v table 5.50 lcd characteristics conditions: vcc = avcc0 = vcc_usb = 2.5 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions lcd drive voltage v l4 2.5 D vcc v
r01ds0216ej0102 rev.1.02 page 106 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.9.2 internal volt age boosting method (1) 1/3 bias method note 1. this is the required wait time from when the reference voltage is specified by the vlcd r egister (or when the internal v oltage boosting method is selected (lcdm0.mdset1 and mdset0 = 01b) if the default reference voltage value is used) until voltage boosting starts (vlcon = 1). note 2. this is the wait time from when voltage boosting is started (vlcon = 1) until display is enabled (lcdon = 1). table 5.51 internal voltage boosting method conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions external capacitance connected between caph and capl pins c1 0.33 0.47 0.61 f external capacitor connected to v l1 pin c2 0.33 0.47 0.61 f external capacitor connected to v l2 pin c3 0.33 0.47 0.61 f external capacitor connected to v l3 pin c4 0.33 0.47 0.61 f external capacitor connected to v l4 pin c5 0.33 0.47 0.61 f table 5.52 internal voltage boosting method lcd characteristics conditions: vcc = avcc0 = vcc_usb = 1.8 v to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol conditions min. typ. max. unit test conditions lcd output voltage variation range v l1 c1 to c4 connected vlcd = 04h 0.9 1.0 1.08 v vlcd = 05h 0.95 1.05 1.13 v vlcd = 06h 1 1.1 1.18 v vlcd = 07h 1.05 1.15 1.23 v vlcd = 08h 1.1 1.2 1.28 v vlcd = 09h 1.15 1.25 1.33 v vlcd = 0ah 1.2 1.3 1.38 v vlcd = 0bh 1.25 1.35 1.43 v vlcd = 0ch 1.3 1.4 1.48 v vlcd = 0dh 1.35 1.45 1.53 v vlcd = 0eh 1.4 1.5 1.58 v vlcd = 0fh 1.45 1.55 1.63 v vlcd = 10h 1.5 1.6 1.68 v vlcd = 11h 1.55 1.65 1.73 v vlcd = 12h 1.6 1.70 1.78 v vlcd = 13h 1.65 1.75 1.83 v doubler output voltage v l2 c1 to c3, c5 connected 2v l1 - 0.10 2v l1 2v l1 v tripler output voltage v l3 c1 to c5 connected 3v l1 - 0.15 3v l1 3v l1 v reference voltage setup time* 1 t vl1s 5??ms lcd output voltage variation range* 2 t vlwt c1 to c4 connected 500 ? ? ms
r01ds0216ej0102 rev.1.02 page 107 of 121 dec 01, 2014 rx113 group 5. electrical characteristics (2) 1/4 bias method note 1. this is the required wait time from when the reference voltage is specified by the vlcd r egister (or when the internal v oltage boosting method is selected (lcdm0.mdset1 and mdset0 = 01b) if the default reference voltage value is used) until voltage boosting starts (vlcon = 1). note 2. this is the wait time from when voltage boosting is started (vlcon = 1) until display is enabled (lcdon = 1). 5.9.3 capacitor split method (1) 1/3 bias method note 1. this is the wait time from when voltage bucking is started (vlcon = 1) until display is enabled (lcdon = 1). table 5.53 internal voltage boosting method lcd characteristics conditions: vcc = avcc0 = vcc_usb = 1.8 v to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol conditions min. typ. max. unit test conditions lcd output voltage variation range v l1 c1 to c4 connected vlcd = 04h 0.9 1.0 1.08 v vlcd = 05h 0.95 1.05 1.13 v vlcd = 06h 1 1.1 1.18 v vlcd = 07h 1.05 1.15 1.23 v vlcd = 08h 1.1 1.2 1.28 v vlcd = 09h 1.15 1.25 1.33 v vlcd = 0ah 1.2 1.3 1.38 v doubler output voltage v l2 c1 to c5 connected 2v l1 - 0.08 2v l1 2v l1 v tripler output voltage v l3 c1 to c5 connected 3v l1 - 0.12 3v l1 3v l1 v quadruply output voltage v l4 c1 to c5 connected 4v l1 - 0.16 4v l1 4v l1 v reference voltage setup time* 1 t vl1s 5??ms voltage boost wait time* 2 t vlwt c1 to c5 connected 500 ? ? ms table 5.54 capacitor split method conditions: vcc = avcc0 = vcc_usb = 2.2 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions external capacitance connected between caph and capl pins c1 0.33 0.47 0.61 f external capacitor connected to v l1 pin c2 0.33 0.47 0.61 f external capacitor connected to v l2 pin c3 0.33 0.47 0.61 f external capacitor connected to v l3 pin c4 0.33 0.47 0.61 f external capacitor connected to v l4 pin c5 0.33 0.47 0.61 f table 5.55 capacitor split method lcd characteristics conditions: vcc = avcc0 = vcc_usb = 2.2 to 3.6v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol conditions min. typ. max. unit test conditions v l4 voltage* 1 v l4 c1 to c4 connected ? vcc ? v v l2 voltage* 1 v l2 c1 to c4 connected 2/3v l4 -0.07 2/3v l4 2/3v l4 +0.07 v v l1 voltage** 1 v l1 c1 to c4 connected 1/3v l4 -0.08 2/3v l4 2/3v l4 +0.08 v capacitor split wait time* 1 t wait 100 ? ? ms
r01ds0216ej0102 rev.1.02 page 108 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.61 lcd reference voltage setup time, vo ltage boosting wait time, and capacitor split wait time 5.10 ctsu characteristics table 5.56 ctsu characteristics conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions external capacitance connected to tscap pin c tscap 91011nf ts pin capacitive load c base ? ? 50 pf 00b 01b or 10b t vl1s t vlwt , t wait mdset1, mdset0 vlcon lcdon
r01ds0216ej0102 rev.1.02 page 109 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.11 power-on reset circuit and voltage detection circuit characteristics note: these characteristics apply when noise is not superimposed on the power supply. wh en a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd2), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. n in the symbol vdet1_n denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note: these characteristics apply when noise is not superimposed on the power supply. wh en a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd1), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. n in the symbol vdet2_n denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. note 2. vdet2_3 selection can be used only when the cmpa2 pin input voltage is selected and cannot be used when the power supply voltage (vcc) is selected. note 3. when ofs1.(stuplvd1ren, faststup) = 11b. note 4. when ofs1.(stuplvd1ren, faststup) 11b. note 5. the minimum vcc down time indicates the time when vcc is below the minimum val ue of voltage detection levels v por , v det0 , v det1, and v det2 for the por/lvd. table 5.57 power-on reset circuit and volt age detection circuit characteristics (1) conditions: vcc = avcc0 = vcc_usb, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 1.35 1.50 1.65 v figure 5.62, figure 5.63 voltage detection circuit (lvd1)* 1 v det1_4 3.00 3.10 3.20 v figure 5.64 at falling edge vcc v det1_5 2.91 3.00 3.09 v det1_6 2.81 2.90 2.99 v det1_7 2.70 2.79 2.88 v det1_8 2.60 2.68 2.76 v det1_9 2.50 2.58 2.66 v det1_a 2.40 2.48 2.56 v det1_b 1.99 2.06 2.13 v det1_c 1.90 1.96 2.02 v det1_d 1.80 1.86 1.92 table 5.58 power-on reset circuit and volt age detection circuit characteristics (2) conditions: vcc = avcc0 = vcc_usb, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level voltage detection circuit (lvd2)* 1 v det2_0 2.71 2.90 3.09 v figure 5.65 at falling edge vcc v det2_1 2.43 2.60 2.77 v det2_2 1.87 2.00 2.13 v det2_3 * 2 1.69 1.80 1.91 wait time after power-on reset cancellation at normal startup* 3 t por D 9.1 D ms figure 5.63 during fast startup time* 4 t por D 1.6 D wait time after voltage monitoring 1 reset cancellation power-on voltage monitoring 1 reset disabled* 3 t lvd1 D 568 D s figure 5.64 power-on voltage monitoring 1 reset enabled* 4 D 100 D wait time after voltage monitoring 2 reset cancellation t lvd2 D 100 D s figure 5.65 response delay time t det DD 350 s figure 5.62 minimum vcc down time* 5 t voff 350 DD s figure 5.62, vcc = 1.0 v or above power-on reset enable time t w (por) 1 DD ms figure 5.63, vcc = below 1.0 v lvd operation stabilization time (after lvd is enabled) td (e-a) DD 300 s figure 5.64, figure 5.65 hysteresis width (lvd1 and lvd2) v lvh D 70 D mv vdet1_4 selected D 60 D vdet1_5 to 9, lvd2 selected D 50 D when selection is from among vdet1_a to b. D 40 D when selection is from among vdet1_c to d.
r01ds0216ej0102 rev.1.02 page 110 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.62 voltage detection reset timing figure 5.63 power-on reset timing internal reset signal (active-low) vcc t voff t por t det v por t det 1.0 v internal reset signal (active-low) vcc t por v por 1.0 v t w(por) *1 t det note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (1.0 v). when vcc turns on, maintain t w(por) for 1.0 ms or more.
r01ds0216ej0102 rev.1.02 page 111 of 121 dec 01, 2014 rx113 group 5. electrical characteristics figure 5.64 voltage detection circuit timing (v det1 ) figure 5.65 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0216ej0102 rev.1.02 page 112 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.12 oscillation stop detection timing figure 5.66 oscillation stop detection timing table 5.59 oscillation stop detection circuit characteristics conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = vss_usb = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.66 t dr main clock or pll clock ostdsr.ostdf loco clock iclk
r01ds0216ej0102 rev.1.02 page 113 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.13 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 10 00), erasing can be performed n times for each bl ock. for instance, when 4-byte programming is performed 256 times for different addresses in 1-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when usi ng the flash memory programmer. note 3. this result is obtained from reliability testing. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. confirm the frequency accuracy of the clock source. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. confirm the frequency accuracy of the clock source. table 5.60 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data hold time after 1000 times of n pec t drp 20* 2, * 3 ? ? year t a = +85c table 5.61 rom (flash memory for code storage) characteristics (2) high-speed operating mode conditions: vcc = avcc0 = v cc_usb = 2.7 to 3.6 v, vs s = avss0 = vss_usb = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 4-byte t p4 ? 103 931 ? 52 489 s erasure time 1-kbyte t e1k ? 8.23 267 ? 5.48 214 ms blank check time 4-byte t bc4 ? ? 48 ? ? 15.9 s 1-kbyte t bc1k ? ? 1.58 ? ? 0.127 ms erase operation forcible stop time t sed ? ? 21.6 ? ? 12.8 s start-up area switching setting time t sas ? 12.6 543 ? 6.16 432 ms access window time t aws ? 12.6 543 ? 6.16 432 ms rom mode transition wait time 1 t dis 2??2?? s rom mode transition wait time 2 t ms 5??5?? s table 5.62 rom (flash memory for code storage) characteristics (3) middle-speed operating mode conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vs s = avss0 = vss_usb = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 4-byte t p4 ? 143 1330 ? 96.8 932 s erasure time 1-kbyte t e1k ? 8.3 269 ? 5.85 219 ms blank check time 4-byte t bc4 ??78?? 50 s 1-kbyte t bc1k ? ? 1.61 ? ? 0.369 ms erase operation forcible stop time t sed ? ? 33.6 ? ? 25.6 s start-up area switching setting time t sas ? 13.2 549 ? 7.6 445 ms access window time t aws ? 13.2 549 ? 7.6 445 ms rom mode transition wait time 1 t dis 2??2? ? s rom mode transition wait time 2 t ms 3??3? ? s
r01ds0216ej0102 rev.1.02 page 114 of 121 dec 01, 2014 rx113 group 5. electrical characteristics 5.14 e2 dataflash characteristics note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 1-byte programming is performed 1000 times for different addresses in 1-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (ove rwriting is prohibited). note 2. characteristics when using the flash memory programmer. note 3. these results are obtained from reliability testing. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. confirm the frequency accuracy of the clock source. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. confirm the frequency accuracy of the clock source. table 5.63 e2 dataflash characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n dpec 100000 1000000 ? times data hold time after 10000 times of n dpec t ddrp 20* 2, * 3 ? ? year t a = +85c after 100000 times of n dpec 5* 2, * 3 ? ? year after 1000000 times of n dpec ?1* 2, * 3 ? year t a = +25c table 5.64 e2 dataflash characteristics (2) : high-speed operating mode conditions: vcc = avcc0 = vcc_usb = 2.7 to 3.6 v, vss = avss0 = usb_vss = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 1-byte t dp1 ? 86 761 ? 40.5 374 s erasure time 1-kbyte t de1k ? 17.4 456 ? 6.15 228 ms blank check time 1-byte t dbc1 ? ? 48 ? ? 15.9 s 1-kbyte t dbc1k ? ? 1.58 ? ? 0.127 ms erase operation forcible stop time t dsed ? ? 21.5 ? ? 12.8 s dataflash stop recovery time t dstop 5??5?? s table 5.65 e2 dataflash characteristics (3) : middle-speed operating mode conditions: vcc = avcc0 = vcc_usb = 1.8 to 3.6 v, vss = avss0 = usb_vss = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 1-byte t dp1 ? 126 1160 ? 85.4 818 s erasure time 1-kbyte t de1k ? 17.5 457 ? 7.76 259 ms blank check time 1-byte t dbc1 ? ? 78 ? ? 50 s 1-kbyte t dbc1k ? ? 1.61 ? ? 0.369 ms erase operation forcible stop time t dsed ? ? 33.5 ? ? 25.5 s dataflash stop recovery time t dstop 720 ? ? 720 ? ? ns
r01ds0216ej0102 rev.1.02 page 115 of 121 dec 01, 2014 rx113 group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 100-pin lfqfp (plqp0100kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lfqfp100-14x14-0.50 e y s s
r01ds0216ej0102 rev.1.02 page 116 of 121 dec 01, 2014 rx113 group appendix 1. package dimensions figure b 100-pin tflga (ptlg0100ja-a) p-tflga100-7x7-0.65 0.1g mass[typ.] 100f0g ptlg0100ja-a renesas code jeita package code previous code 0.15 v 0.20 w 0.08 0.485 0.435 0.385 max nom min dimension in millimeters symbol reference 7.0 d 7.0 e 1.05 a x 0.65 e 0.10 y b 1 b0 . 31 0. 35 0.39 0.575 z d z e 0.575 index mark b w s w a s a h g f e d c b 1234 5678 ys s a v 4 (laser mark) index mark j k 910 d e e e a z d z e b b b 1 ms ab ms ab
r01ds0216ej0102 rev.1.02 page 117 of 121 dec 01, 2014 rx113 group appendix 1. package dimensions figure c 64-pin lfqfp (plqp0064kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lfqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.250.200.15 maxnommin dimension in millimeters symbol reference 10.110.0 9.9 d 10.110.0 9.9 e 1.4 a 2 12.212.011.8 12.212.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
r01ds0216ej0102 rev.1.02 page 118 of 121 dec 01, 2014 rx113 group revision history revision history rx113 group datasheet rev. date description page summary 1.02 dec 01, 2014 ? first edition, issued all trademarks and registered trademarks are the property of their respective owners. revision history
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-ku, seoul, 135-920, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2014 renesas electronics corporation. all rights reserved. colophon 4.0

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